ADC_CTRL Simulation Results

Wednesday September 18 2024 00:48:27 UTC

GitHub Revision: `7e34e67ade`

Branch: os_regression_2024_09_17

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 4190660412037082522497784440658734031572790705268868319466386425736861254975

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	26.960s	5.977ms	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	4.370s	1.089ms	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	3.110s	525.410us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	53.400s	24.942ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	5.820s	919.262us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	3.360s	432.422us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	3.110s	525.410us	20	20	100.00
		adc_ctrl_csr_aliasing	5.820s	919.262us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	24.675m	489.714ms	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	26.779m	495.973ms	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	25.250m	501.928ms	50	50	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	23.384m	500.286ms	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	26.816m	549.093ms	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	30.633m	616.171ms	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	25.797m	538.099ms	49	50	98.00
V2	clock_gating	adc_ctrl_clock_gating	24.351m	514.846ms	50	50	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	22.890s	4.994ms	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	2.439m	38.565ms	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	16.822m	126.098ms	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	1.564h	1.876s	50	50	100.00
V2	alert_test	adc_ctrl_alert_test	3.010s	478.905us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	2.690s	447.908us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	4.030s	1.131ms	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	4.030s	1.131ms	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	4.370s	1.089ms	5	5	100.00
		adc_ctrl_csr_rw	3.110s	525.410us	20	20	100.00
		adc_ctrl_csr_aliasing	5.820s	919.262us	5	5	100.00
		adc_ctrl_same_csr_outstanding	19.360s	4.701ms	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	4.370s	1.089ms	5	5	100.00
		adc_ctrl_csr_rw	3.110s	525.410us	20	20	100.00
		adc_ctrl_csr_aliasing	5.820s	919.262us	5	5	100.00
		adc_ctrl_same_csr_outstanding	19.360s	4.701ms	20	20	100.00
V2		TOTAL			739	740	99.86
V2S	tl_intg_err	adc_ctrl_sec_cm	30.730s	7.881ms	5	5	100.00
		adc_ctrl_tl_intg_err	24.260s	8.422ms	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	24.260s	8.422ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	48.200s	18.245ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			919	920	99.89

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	16	16	15	93.75
V2S	2	2	2	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.70	99.07	96.67	100.00	100.00	98.82	98.33	90.99

Failure Buckets

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test adc_ctrl_filters_both has 1 failures.
  - 42.adc_ctrl_filters_both.48319243165782919686693318133778401206026386772894117739799973441676876741418
    Line 170, in log /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/42.adc_ctrl_filters_both/latest/run.log
```
  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ADC_CTRL Simulation Results

Wednesday September 18 2024 00:48:27 UTC

GitHub Revision: 7e34e67ade

Branch: os_regression_2024_09_17

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 4190660412037082522497784440658734031572790705268868319466386425736861254975

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `7e34e67ade`