ADC_CTRL Simulation Results

Friday October 11 2024 20:19:09 UTC

GitHub Revision: 8a1401d614

Branch: os_regression_2024_10_11

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 53663846044628477120113920685171085698887397097422685916033931805982305505364

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	27.090s	5.606ms	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	6.110s	1.165ms	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	4.140s	572.319us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	1.938m	45.854ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	7.010s	980.068us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	4.560s	540.728us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	4.140s	572.319us	20	20	100.00
		adc_ctrl_csr_aliasing	7.010s	980.068us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	27.833m	495.720ms	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	25.864m	492.864ms	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	21.895m	499.439ms	50	50	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	26.322m	499.040ms	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	28.049m	621.601ms	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	36.248m	592.876ms	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	25.779m	600.000ms	48	50	96.00
V2	clock_gating	adc_ctrl_clock_gating	24.495m	492.790ms	50	50	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	24.070s	5.500ms	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	3.194m	47.698ms	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	16.903m	111.518ms	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	54.503m	1.470s	50	50	100.00
V2	alert_test	adc_ctrl_alert_test	3.220s	530.661us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	3.360s	518.140us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	4.580s	552.410us	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	4.580s	552.410us	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	6.110s	1.165ms	5	5	100.00
		adc_ctrl_csr_rw	4.140s	572.319us	20	20	100.00
		adc_ctrl_csr_aliasing	7.010s	980.068us	5	5	100.00
		adc_ctrl_same_csr_outstanding	23.950s	4.477ms	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	6.110s	1.165ms	5	5	100.00
		adc_ctrl_csr_rw	4.140s	572.319us	20	20	100.00
		adc_ctrl_csr_aliasing	7.010s	980.068us	5	5	100.00
		adc_ctrl_same_csr_outstanding	23.950s	4.477ms	20	20	100.00
V2		TOTAL			738	740	99.73
V2S	tl_intg_err	adc_ctrl_sec_cm	34.160s	7.349ms	5	5	100.00
		adc_ctrl_tl_intg_err	33.670s	8.399ms	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	33.670s	8.399ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	1.900m	44.577ms	49	50	98.00
V3		TOTAL			49	50	98.00
		TOTAL			917	920	99.67

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	16	16	15	93.75
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.70	99.07	96.67	100.00	100.00	98.82	98.33	90.99

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:

  • Test adc_ctrl_filters_both has 2 failures.

    • 38.adc_ctrl_filters_both.38158146660859588371357432145933743640581789145151683609363638071133644570923
      Line 170, in log /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/38.adc_ctrl_filters_both/latest/run.log

        UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 41.adc_ctrl_filters_both.58336329127475284010107065556112457370873740078865675717337480758676171950718
      Line 170, in log /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/41.adc_ctrl_filters_both/latest/run.log

        UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(np_sample_cnt_q == '0)' has 1 failures:

  • Test adc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 15.adc_ctrl_stress_all_with_rand_reset.5552330916752486535222805984264609238973704192383916601400815791233185983165
      Line 250, in log /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/15.adc_ctrl_stress_all_with_rand_reset/latest/run.log

            Offending '(np_sample_cnt_q == '0)'
        UVM_ERROR @ 14562436544 ps: (adc_ctrl_fsm.sv:384) [ASSERT FAILED] NpCntClrPwrDn_A
        UVM_INFO @ 14562436544 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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