AES/MASKED Simulation Results

Monday May 22 2023 07:05:49 UTC

GitHub Revision: `e3fb01b5e`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 3641199223

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	113.708us	1	1	100.00
V1	smoke	aes_smoke	6.000s	86.304us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	70.319us	5	5	100.00
V1	csr_rw	aes_csr_rw	3.000s	72.523us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	11.000s	3.599ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	269.504us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	4.000s	90.217us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	3.000s	72.523us	20	20	100.00
		aes_csr_aliasing	5.000s	269.504us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	6.000s	86.304us	50	50	100.00
		aes_config_error	31.000s	1.109ms	50	50	100.00
		aes_stress	2.117m	3.096ms	50	50	100.00
V2	key_length	aes_smoke	6.000s	86.304us	50	50	100.00
		aes_config_error	31.000s	1.109ms	50	50	100.00
		aes_stress	2.117m	3.096ms	50	50	100.00
V2	back2back	aes_stress	2.117m	3.096ms	50	50	100.00
		aes_b2b	41.000s	978.680us	50	50	100.00
V2	backpressure	aes_stress	2.117m	3.096ms	50	50	100.00
V2	multi_message	aes_smoke	6.000s	86.304us	50	50	100.00
		aes_config_error	31.000s	1.109ms	50	50	100.00
		aes_stress	2.117m	3.096ms	50	50	100.00
		aes_alert_reset	18.000s	723.946us	50	50	100.00
V2	failure_test	aes_config_error	31.000s	1.109ms	50	50	100.00
		aes_alert_reset	18.000s	723.946us	50	50	100.00
		aes_man_cfg_err	5.000s	140.772us	50	50	100.00
V2	trigger_clear_test	aes_clear	1.500m	3.189ms	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	11.000s	445.295us	1	1	100.00
V2	reset_recovery	aes_alert_reset	18.000s	723.946us	50	50	100.00
V2	stress	aes_stress	2.117m	3.096ms	50	50	100.00
V2	sideload	aes_stress	2.117m	3.096ms	50	50	100.00
		aes_sideload	13.000s	857.955us	50	50	100.00
V2	deinitialization	aes_deinit	12.000s	382.915us	50	50	100.00
V2	alert_test	aes_alert_test	5.000s	88.643us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	5.000s	138.373us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	5.000s	138.373us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	70.319us	5	5	100.00
		aes_csr_rw	3.000s	72.523us	20	20	100.00
		aes_csr_aliasing	5.000s	269.504us	5	5	100.00
		aes_same_csr_outstanding	4.000s	337.658us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	70.319us	5	5	100.00
		aes_csr_rw	3.000s	72.523us	20	20	100.00
		aes_csr_aliasing	5.000s	269.504us	5	5	100.00
		aes_same_csr_outstanding	4.000s	337.658us	20	20	100.00
V2		TOTAL			491	491	100.00
V2S	reseeding	aes_reseed	5.083m	4.401ms	50	50	100.00
V2S	fault_inject	aes_fi	48.000s	4.546ms	49	50	98.00
		aes_control_fi	33.000s	10.005ms	269	300	89.67
		aes_cipher_fi	52.000s	10.005ms	338	350	96.57
V2S	shadow_reg_update_error	aes_shadow_reg_errors	3.000s	79.082us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	3.000s	79.082us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	3.000s	79.082us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	3.000s	79.082us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	5.000s	194.113us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	9.000s	4.092ms	5	5	100.00
		aes_tl_intg_err	5.000s	155.506us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	5.000s	155.506us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	18.000s	723.946us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	3.000s	79.082us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	6.000s	86.304us	50	50	100.00
		aes_stress	2.117m	3.096ms	50	50	100.00
		aes_alert_reset	18.000s	723.946us	50	50	100.00
		aes_core_fi	1.467m	10.003ms	67	70	95.71
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	3.000s	79.082us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_stress	2.117m	3.096ms	50	50	100.00
		aes_readability	6.000s	231.313us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	2.117m	3.096ms	50	50	100.00
		aes_sideload	13.000s	857.955us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	6.000s	231.313us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	6.000s	231.313us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	6.000s	231.313us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	6.000s	231.313us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	6.000s	231.313us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	2.117m	3.096ms	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	2.117m	3.096ms	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	48.000s	4.546ms	49	50	98.00
V2S	sec_cm_main_fsm_redun	aes_fi	48.000s	4.546ms	49	50	98.00
		aes_control_fi	33.000s	10.005ms	269	300	89.67
		aes_cipher_fi	52.000s	10.005ms	338	350	96.57
		aes_ctr_fi	5.000s	134.636us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	48.000s	4.546ms	49	50	98.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	48.000s	4.546ms	49	50	98.00
		aes_control_fi	33.000s	10.005ms	269	300	89.67
		aes_cipher_fi	52.000s	10.005ms	338	350	96.57
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	52.000s	10.005ms	338	350	96.57
V2S	sec_cm_ctr_fsm_sparse	aes_fi	48.000s	4.546ms	49	50	98.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	48.000s	4.546ms	49	50	98.00
		aes_control_fi	33.000s	10.005ms	269	300	89.67
		aes_ctr_fi	5.000s	134.636us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	48.000s	4.546ms	49	50	98.00
		aes_control_fi	33.000s	10.005ms	269	300	89.67
		aes_cipher_fi	52.000s	10.005ms	338	350	96.57
		aes_ctr_fi	5.000s	134.636us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	18.000s	723.946us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	48.000s	4.546ms	49	50	98.00
		aes_control_fi	33.000s	10.005ms	269	300	89.67
		aes_cipher_fi	52.000s	10.005ms	338	350	96.57
		aes_ctr_fi	5.000s	134.636us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	48.000s	4.546ms	49	50	98.00
		aes_control_fi	33.000s	10.005ms	269	300	89.67
		aes_cipher_fi	52.000s	10.005ms	338	350	96.57
		aes_ctr_fi	5.000s	134.636us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	48.000s	4.546ms	49	50	98.00
		aes_control_fi	33.000s	10.005ms	269	300	89.67
		aes_ctr_fi	5.000s	134.636us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	48.000s	4.546ms	49	50	98.00
		aes_control_fi	33.000s	10.005ms	269	300	89.67
		aes_cipher_fi	52.000s	10.005ms	338	350	96.57
V2S		TOTAL			938	985	95.23
V3		TOTAL			0	0	--
		TOTAL			1535	1582	97.03

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	12	12	12	100.00
V2S	11	11	7	63.64

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.46	99.00	97.51	99.42	95.92	95.60	97.78	98.67	91.89

Failure Buckets

Job aes_masked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 31 failures:
- Test aes_control_fi has 26 failures.
  - 4.aes_control_fi.2768856900
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/4.aes_control_fi/latest/run.log
```
  Job ID: smart:24de3874-3985-4327-b354-52ada0f44804
```
  - 23.aes_control_fi.735822383
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/23.aes_control_fi/latest/run.log
```
  Job ID: smart:20a53d7b-d4a4-42e2-8c47-8c8c46caf235
```
  - ... and 24 more failures.
- Test aes_cipher_fi has 5 failures.
  - 86.aes_cipher_fi.1766901147
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/86.aes_cipher_fi/latest/run.log
```
  Job ID: smart:65699198-469c-456e-95a2-6811c295922f
```
  - 171.aes_cipher_fi.2668540099
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/171.aes_cipher_fi/latest/run.log
```
  Job ID: smart:4b98e725-981c-40a7-9325-0fef623a9552
```
  - ... and 3 more failures.

UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 7 failures:

Test aes_cipher_fi has 7 failures.

44.aes_cipher_fi.1587647521
Line 285, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/44.aes_cipher_fi/latest/run.log

  UVM_FATAL @ 10031566404 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10031566404 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

59.aes_cipher_fi.4125230621
Line 282, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/59.aes_cipher_fi/latest/run.log

  UVM_FATAL @ 10010629226 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10010629226 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 5 failures:

Test aes_control_fi has 5 failures.

1.aes_control_fi.846201207
Line 283, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_control_fi/latest/run.log

  UVM_FATAL @ 10034636140 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10034636140 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

9.aes_control_fi.3302991513
Line 292, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/9.aes_control_fi/latest/run.log

  UVM_FATAL @ 10027745178 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10027745178 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:

Test aes_core_fi has 2 failures.

23.aes_core_fi.884610674
Line 286, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/23.aes_core_fi/latest/run.log

  UVM_FATAL @ 10008306977 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10008306977 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

49.aes_core_fi.4291498055
Line 285, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/49.aes_core_fi/latest/run.log

  UVM_FATAL @ 10003467531 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10003467531 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,978): Assertion AesSecCmDataRegLocalEscDataOut has failed (* cycles, starting * PS) has 1 failures:

Test aes_fi has 1 failures.

31.aes_fi.305551175
Line 607, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/31.aes_fi/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,978): (time 14622020 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 14601187 PS)
        ($past(iv_q) != $past(state_done_transposed, 2) ^ $past(data_in_prev_q, 2)))
                                                                                   |
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,984): (time 14622020 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 14601187 PS)
  UVM_ERROR @  14622020 ps: (aes_core.sv:978) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut

UVM_FATAL (aes_core_fi_vseq.sv:89) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 47.aes_core_fi.1210835381
    Line 273, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/47.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10013745564 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10013745564 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```