AES/MASKED Simulation Results

Sunday October 15 2023 19:02:25 UTC

GitHub Revision: `b2a255f8a`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 1600673825

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	59.973us	1	1	100.00
V1	smoke	aes_smoke	7.000s	171.790us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	6.000s	74.957us	5	5	100.00
V1	csr_rw	aes_csr_rw	9.000s	61.093us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	14.000s	1.505ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	8.000s	604.198us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	13.000s	59.357us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	9.000s	61.093us	20	20	100.00
		aes_csr_aliasing	8.000s	604.198us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	7.000s	171.790us	50	50	100.00
		aes_config_error	24.000s	741.982us	50	50	100.00
		aes_stress	20.000s	554.327us	50	50	100.00
V2	key_length	aes_smoke	7.000s	171.790us	50	50	100.00
		aes_config_error	24.000s	741.982us	50	50	100.00
		aes_stress	20.000s	554.327us	50	50	100.00
V2	back2back	aes_stress	20.000s	554.327us	50	50	100.00
		aes_b2b	27.000s	3.689ms	50	50	100.00
V2	backpressure	aes_stress	20.000s	554.327us	50	50	100.00
V2	multi_message	aes_smoke	7.000s	171.790us	50	50	100.00
		aes_config_error	24.000s	741.982us	50	50	100.00
		aes_stress	20.000s	554.327us	50	50	100.00
		aes_alert_reset	1.067m	4.490ms	50	50	100.00
V2	failure_test	aes_man_cfg_err	8.000s	118.984us	50	50	100.00
		aes_config_error	24.000s	741.982us	50	50	100.00
		aes_alert_reset	1.067m	4.490ms	50	50	100.00
V2	trigger_clear_test	aes_clear	19.000s	2.125ms	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	17.000s	173.195us	1	1	100.00
V2	reset_recovery	aes_alert_reset	1.067m	4.490ms	50	50	100.00
V2	stress	aes_stress	20.000s	554.327us	50	50	100.00
V2	sideload	aes_stress	20.000s	554.327us	50	50	100.00
		aes_sideload	15.000s	1.057ms	50	50	100.00
V2	deinitialization	aes_deinit	9.000s	134.922us	50	50	100.00
V2	stress_all	aes_stress_all	2.050m	10.199ms	10	10	100.00
V2	alert_test	aes_alert_test	8.000s	51.912us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	9.000s	247.392us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	9.000s	247.392us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	6.000s	74.957us	5	5	100.00
		aes_csr_rw	9.000s	61.093us	20	20	100.00
		aes_csr_aliasing	8.000s	604.198us	5	5	100.00
		aes_same_csr_outstanding	8.000s	261.731us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	6.000s	74.957us	5	5	100.00
		aes_csr_rw	9.000s	61.093us	20	20	100.00
		aes_csr_aliasing	8.000s	604.198us	5	5	100.00
		aes_same_csr_outstanding	8.000s	261.731us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	52.000s	1.695ms	50	50	100.00
V2S	fault_inject	aes_fi	11.000s	351.071us	50	50	100.00
		aes_control_fi	38.000s	10.007ms	288	300	96.00
		aes_cipher_fi	51.000s	10.010ms	342	350	97.71
V2S	shadow_reg_update_error	aes_shadow_reg_errors	13.000s	61.171us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	13.000s	61.171us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	13.000s	61.171us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	13.000s	61.171us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	12.000s	186.116us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	13.000s	1.148ms	5	5	100.00
		aes_tl_intg_err	11.000s	1.339ms	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	11.000s	1.339ms	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	1.067m	4.490ms	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	13.000s	61.171us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	7.000s	171.790us	50	50	100.00
		aes_stress	20.000s	554.327us	50	50	100.00
		aes_alert_reset	1.067m	4.490ms	50	50	100.00
		aes_core_fi	1.483m	10.005ms	68	70	97.14
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	13.000s	61.171us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	9.000s	63.516us	50	50	100.00
		aes_stress	20.000s	554.327us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	20.000s	554.327us	50	50	100.00
		aes_sideload	15.000s	1.057ms	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	9.000s	63.516us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	9.000s	63.516us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	9.000s	63.516us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	9.000s	63.516us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	9.000s	63.516us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	20.000s	554.327us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	20.000s	554.327us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	11.000s	351.071us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	11.000s	351.071us	50	50	100.00
		aes_control_fi	38.000s	10.007ms	288	300	96.00
		aes_cipher_fi	51.000s	10.010ms	342	350	97.71
		aes_ctr_fi	4.000s	165.554us	49	50	98.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	11.000s	351.071us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	11.000s	351.071us	50	50	100.00
		aes_control_fi	38.000s	10.007ms	288	300	96.00
		aes_cipher_fi	51.000s	10.010ms	342	350	97.71
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	51.000s	10.010ms	342	350	97.71
V2S	sec_cm_ctr_fsm_sparse	aes_fi	11.000s	351.071us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	11.000s	351.071us	50	50	100.00
		aes_control_fi	38.000s	10.007ms	288	300	96.00
		aes_ctr_fi	4.000s	165.554us	49	50	98.00
V2S	sec_cm_ctrl_sparse	aes_fi	11.000s	351.071us	50	50	100.00
		aes_control_fi	38.000s	10.007ms	288	300	96.00
		aes_cipher_fi	51.000s	10.010ms	342	350	97.71
		aes_ctr_fi	4.000s	165.554us	49	50	98.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	1.067m	4.490ms	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	11.000s	351.071us	50	50	100.00
		aes_control_fi	38.000s	10.007ms	288	300	96.00
		aes_cipher_fi	51.000s	10.010ms	342	350	97.71
		aes_ctr_fi	4.000s	165.554us	49	50	98.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	11.000s	351.071us	50	50	100.00
		aes_control_fi	38.000s	10.007ms	288	300	96.00
		aes_cipher_fi	51.000s	10.010ms	342	350	97.71
		aes_ctr_fi	4.000s	165.554us	49	50	98.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	11.000s	351.071us	50	50	100.00
		aes_control_fi	38.000s	10.007ms	288	300	96.00
		aes_ctr_fi	4.000s	165.554us	49	50	98.00
V2S	sec_cm_data_reg_local_esc	aes_fi	11.000s	351.071us	50	50	100.00
		aes_control_fi	38.000s	10.007ms	288	300	96.00
		aes_cipher_fi	51.000s	10.010ms	342	350	97.71
V2S		TOTAL			962	985	97.66
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	4.383m	34.470ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1569	1602	97.94

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	13	100.00
V2S	11	11	7	63.64
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.52	99.01	97.51	99.42	95.76	95.66	97.78	98.97	98.38

Failure Buckets

Job aes_masked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 12 failures:
- Test aes_ctr_fi has 1 failures.
  - 49.aes_ctr_fi.3219585513
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/49.aes_ctr_fi/latest/run.log
```
  Job ID: smart:9e378656-81ab-4575-9343-1a069b8e9420
```
- Test aes_control_fi has 8 failures.
  - 52.aes_control_fi.3419345898
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/52.aes_control_fi/latest/run.log
```
  Job ID: smart:6b5ab2d8-1062-4413-ba9a-06aa961194b0
```
  - 111.aes_control_fi.1960151823
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/111.aes_control_fi/latest/run.log
```
  Job ID: smart:efa44177-9952-450f-9006-88707b753a70
```
  - ... and 6 more failures.
- Test aes_cipher_fi has 3 failures.
  - 107.aes_cipher_fi.1506269087
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/107.aes_cipher_fi/latest/run.log
```
  Job ID: smart:1acb9041-13aa-47bc-85c9-eb4a6aae7860
```
  - 171.aes_cipher_fi.3019272454
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/171.aes_cipher_fi/latest/run.log
```
  Job ID: smart:c1cb1783-734f-4ea7-a88e-b9b69db8615f
```
  - ... and 1 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 8 failures:

Test aes_stress_all_with_rand_reset has 8 failures.

0.aes_stress_all_with_rand_reset.1354627220
Line 931, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2083022199 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 2083022199 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.2073180550
Line 841, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 34470087251 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 34470087251 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 5 failures:

Test aes_cipher_fi has 5 failures.

31.aes_cipher_fi.2297517226
Line 283, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/31.aes_cipher_fi/latest/run.log

  UVM_FATAL @ 10010160808 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10010160808 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

142.aes_cipher_fi.2617116712
Line 273, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/142.aes_cipher_fi/latest/run.log

  UVM_FATAL @ 10056029069 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10056029069 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 4 failures:

Test aes_control_fi has 4 failures.

40.aes_control_fi.3132055458
Line 279, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/40.aes_control_fi/latest/run.log

  UVM_FATAL @ 10015493545 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10015493545 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

68.aes_control_fi.3787210394
Line 285, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/68.aes_control_fi/latest/run.log

  UVM_FATAL @ 10011620839 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10011620839 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 2 failures:

Test aes_stress_all_with_rand_reset has 2 failures.

6.aes_stress_all_with_rand_reset.3349258771
Line 429, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/6.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 221531157 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 221531157 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

7.aes_stress_all_with_rand_reset.167958980
Line 1725, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/7.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 3734300312 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 3734300312 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:

Test aes_core_fi has 2 failures.

8.aes_core_fi.572282309
Line 279, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/8.aes_core_fi/latest/run.log

  UVM_FATAL @ 10013748530 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10013748530 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

22.aes_core_fi.1757795600
Line 284, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/22.aes_core_fi/latest/run.log

  UVM_FATAL @ 10004625582 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10004625582 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---