AES/MASKED Simulation Results

Sunday February 18 2024 20:02:30 UTC

GitHub Revision: `8faf04697a`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 18983509472502570446328716692660256492766541929441074968843370054317032656232

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	104.004us	1	1	100.00
V1	smoke	aes_smoke	6.000s	108.753us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	4.000s	158.051us	5	5	100.00
V1	csr_rw	aes_csr_rw	7.000s	506.083us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	10.000s	2.476ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	285.290us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	6.000s	269.329us	18	20	90.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	7.000s	506.083us	20	20	100.00
		aes_csr_aliasing	5.000s	285.290us	5	5	100.00
V1		TOTAL			104	106	98.11
V2	algorithm	aes_smoke	6.000s	108.753us	50	50	100.00
		aes_config_error	35.000s	1.058ms	50	50	100.00
		aes_stress	1.883m	3.599ms	50	50	100.00
V2	key_length	aes_smoke	6.000s	108.753us	50	50	100.00
		aes_config_error	35.000s	1.058ms	50	50	100.00
		aes_stress	1.883m	3.599ms	50	50	100.00
V2	back2back	aes_stress	1.883m	3.599ms	50	50	100.00
		aes_b2b	1.367m	1.008ms	50	50	100.00
V2	backpressure	aes_stress	1.883m	3.599ms	50	50	100.00
V2	multi_message	aes_smoke	6.000s	108.753us	50	50	100.00
		aes_config_error	35.000s	1.058ms	50	50	100.00
		aes_stress	1.883m	3.599ms	50	50	100.00
		aes_alert_reset	16.000s	2.249ms	50	50	100.00
V2	failure_test	aes_man_cfg_err	6.000s	241.543us	50	50	100.00
		aes_config_error	35.000s	1.058ms	50	50	100.00
		aes_alert_reset	16.000s	2.249ms	50	50	100.00
V2	trigger_clear_test	aes_clear	21.000s	2.933ms	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	11.000s	1.814ms	1	1	100.00
V2	reset_recovery	aes_alert_reset	16.000s	2.249ms	50	50	100.00
V2	stress	aes_stress	1.883m	3.599ms	50	50	100.00
V2	sideload	aes_stress	1.883m	3.599ms	50	50	100.00
		aes_sideload	36.000s	1.053ms	50	50	100.00
V2	deinitialization	aes_deinit	13.000s	211.193us	50	50	100.00
V2	stress_all	aes_stress_all	1.083m	836.214us	9	10	90.00
V2	alert_test	aes_alert_test	4.000s	58.510us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	6.000s	240.561us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	6.000s	240.561us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	4.000s	158.051us	5	5	100.00
		aes_csr_rw	7.000s	506.083us	20	20	100.00
		aes_csr_aliasing	5.000s	285.290us	5	5	100.00
		aes_same_csr_outstanding	4.000s	119.513us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	4.000s	158.051us	5	5	100.00
		aes_csr_rw	7.000s	506.083us	20	20	100.00
		aes_csr_aliasing	5.000s	285.290us	5	5	100.00
		aes_same_csr_outstanding	4.000s	119.513us	20	20	100.00
V2		TOTAL			500	501	99.80
V2S	reseeding	aes_reseed	45.000s	1.724ms	50	50	100.00
V2S	fault_inject	aes_fi	41.000s	2.293ms	49	50	98.00
		aes_control_fi	50.000s	10.006ms	282	300	94.00
		aes_cipher_fi	43.000s	10.009ms	342	350	97.71
V2S	shadow_reg_update_error	aes_shadow_reg_errors	3.000s	101.927us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	3.000s	101.927us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	3.000s	101.927us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	3.000s	101.927us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	8.000s	106.067us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	9.000s	5.119ms	5	5	100.00
		aes_tl_intg_err	6.000s	234.482us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	6.000s	234.482us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	16.000s	2.249ms	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	3.000s	101.927us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	6.000s	108.753us	50	50	100.00
		aes_stress	1.883m	3.599ms	50	50	100.00
		aes_alert_reset	16.000s	2.249ms	50	50	100.00
		aes_core_fi	2.017m	10.045ms	66	70	94.29
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	3.000s	101.927us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	4.000s	61.353us	50	50	100.00
		aes_stress	1.883m	3.599ms	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	1.883m	3.599ms	50	50	100.00
		aes_sideload	36.000s	1.053ms	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	4.000s	61.353us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	4.000s	61.353us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	4.000s	61.353us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	4.000s	61.353us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	4.000s	61.353us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	1.883m	3.599ms	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	1.883m	3.599ms	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	41.000s	2.293ms	49	50	98.00
V2S	sec_cm_main_fsm_redun	aes_fi	41.000s	2.293ms	49	50	98.00
		aes_control_fi	50.000s	10.006ms	282	300	94.00
		aes_cipher_fi	43.000s	10.009ms	342	350	97.71
		aes_ctr_fi	5.000s	268.037us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	41.000s	2.293ms	49	50	98.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	41.000s	2.293ms	49	50	98.00
		aes_control_fi	50.000s	10.006ms	282	300	94.00
		aes_cipher_fi	43.000s	10.009ms	342	350	97.71
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	43.000s	10.009ms	342	350	97.71
V2S	sec_cm_ctr_fsm_sparse	aes_fi	41.000s	2.293ms	49	50	98.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	41.000s	2.293ms	49	50	98.00
		aes_control_fi	50.000s	10.006ms	282	300	94.00
		aes_ctr_fi	5.000s	268.037us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	41.000s	2.293ms	49	50	98.00
		aes_control_fi	50.000s	10.006ms	282	300	94.00
		aes_cipher_fi	43.000s	10.009ms	342	350	97.71
		aes_ctr_fi	5.000s	268.037us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	16.000s	2.249ms	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	41.000s	2.293ms	49	50	98.00
		aes_control_fi	50.000s	10.006ms	282	300	94.00
		aes_cipher_fi	43.000s	10.009ms	342	350	97.71
		aes_ctr_fi	5.000s	268.037us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	41.000s	2.293ms	49	50	98.00
		aes_control_fi	50.000s	10.006ms	282	300	94.00
		aes_cipher_fi	43.000s	10.009ms	342	350	97.71
		aes_ctr_fi	5.000s	268.037us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	41.000s	2.293ms	49	50	98.00
		aes_control_fi	50.000s	10.006ms	282	300	94.00
		aes_ctr_fi	5.000s	268.037us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	41.000s	2.293ms	49	50	98.00
		aes_control_fi	50.000s	10.006ms	282	300	94.00
		aes_cipher_fi	43.000s	10.009ms	342	350	97.71
V2S		TOTAL			954	985	96.85
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	1.717m	3.131ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1558	1602	97.25

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	6	85.71
V2	13	13	12	92.31
V2S	11	11	7	63.64
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.59	98.97	97.40	99.45	95.91	97.64	100.00	98.96	96.01

Failure Buckets

Job aes_masked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 12 failures:
- Test aes_control_fi has 9 failures.
  - 55.aes_control_fi.73294055610808433042961881072666058532202542720261559287921512778341114910079
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/55.aes_control_fi/latest/run.log
```
  Job ID: smart:db949906-2fdb-4755-a4fa-380b8a416919
```
  - 86.aes_control_fi.71335633984662759544082439725492810027536839195211521148215330390564964202374
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/86.aes_control_fi/latest/run.log
```
  Job ID: smart:3a813064-8b5f-4b34-a675-17910e4e057a
```
  - ... and 7 more failures.
- Test aes_cipher_fi has 3 failures.
  - 154.aes_cipher_fi.32695769743393220172162827346661528191697011437764774274163301831481887733562
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/154.aes_cipher_fi/latest/run.log
```
  Job ID: smart:63111ce7-c4da-4a21-9f01-1c5f524a2da7
```
  - 219.aes_cipher_fi.41557206995348049289194860800915935106945122208343778757785266429329723730676
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/219.aes_cipher_fi/latest/run.log
```
  Job ID: smart:6843e2ff-0b37-42bf-a1e6-c5beb2f47a5a
```
  - ... and 1 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 9 failures:
- Test aes_control_fi has 9 failures.
  - 28.aes_control_fi.111437318160969939150392675368623024684165135254167888003217384023290022244615
    Line 316, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/28.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10018818595 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10018818595 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 43.aes_control_fi.30463511683294061311040790155337732748828879637627529207103546130764766752545
    Line 313, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/43.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10015605087 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10015605087 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 7 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 5 failures:

Test aes_stress_all_with_rand_reset has 5 failures.

1.aes_stress_all_with_rand_reset.60620720336582963707068318139487493893731970669561495021466001997912183795079
Line 1008, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 3130876140 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 3130876140 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.aes_stress_all_with_rand_reset.21263323457645327201261846711925491859488248319231864061551544631195326769531
Line 1860, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 5932245167 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 5932245167 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 5 failures:
- Test aes_cipher_fi has 5 failures.
  - 106.aes_cipher_fi.64987411730273979251317562595211601698426247326455349979677695403328025326592
    Line 322, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/106.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10051655195 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10051655195 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 152.aes_cipher_fi.11348114791327063915002733052735020410202003537933284106646307114434621606681
    Line 315, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/152.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10005853034 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10005853034 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 3 failures:

Test aes_stress_all_with_rand_reset has 3 failures.

4.aes_stress_all_with_rand_reset.20636324837097504771818071866963340346952930906732915358542527440581733553666
Line 1102, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/4.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1969893757 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1969893757 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.aes_stress_all_with_rand_reset.39976401866123526104812084861031546805678557516375575553701519625338031728804
Line 914, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/5.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 743855212 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 743855212 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL (aes_reseed_vseq.sv:40) [aes_reseed_vseq] Check failed request_seen | finished_all_msgs == *'b* (* [*] vs * [*]) has 2 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 0.aes_stress_all_with_rand_reset.30735260256671306944584472695115111160920578633241618492978324809662605293650
    Line 478, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 491053169 ps: (aes_reseed_vseq.sv:40) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed request_seen | finished_all_msgs == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 491053169 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test aes_stress_all has 1 failures.
  - 6.aes_stress_all.23226597777165234582804580608897324723119726159926176103292240366909204218271
    Line 49814, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/6.aes_stress_all/latest/run.log
```
  UVM_FATAL @ 1053082011 ps: (aes_reseed_vseq.sv:40) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed request_seen | finished_all_msgs == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 1053082011 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:757) [aes_common_vseq] Check failed (!has_outstanding_access()) Outstanding access never cleared to allow us to reset. has 2 failures:
- Test aes_csr_mem_rw_with_rand_reset has 2 failures.
  - 9.aes_csr_mem_rw_with_rand_reset.103367445252774094089982110127599678058334366894860793862382042246036004321245
    Line 291, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/9.aes_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 764767972 ps: (cip_base_vseq.sv:757) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Outstanding access never cleared to allow us to reset.
  UVM_INFO @ 764767972 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 13.aes_csr_mem_rw_with_rand_reset.73913687820658477498223378627159808292941017993997657718851987568523402509210
    Line 291, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/13.aes_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 389514796 ps: (cip_base_vseq.sv:757) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Outstanding access never cleared to allow us to reset.
  UVM_INFO @ 389514796 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_core_fi has 2 failures.
  - 11.aes_core_fi.47870847917197735057403367680245971199597675499828355139829095695943054258353
    Line 317, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/11.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10012648221 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10012648221 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 62.aes_core_fi.52349324233007299161509623743589781807725261098078611779509426827505026234122
    Line 320, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/62.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10012472210 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10012472210 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:572) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=*) == * has 2 failures:
- Test aes_core_fi has 2 failures.
  - 31.aes_core_fi.29899751484095747057662822613383076504670656294919307230310668427045972388925
    Line 312, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/31.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10119026629 ps: (csr_utils_pkg.sv:572) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0x141f0284) == 0x0
  UVM_INFO @ 10119026629 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 49.aes_core_fi.29908162444108979867093063556092049397544242105890816949866991956248991904449
    Line 315, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/49.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10044924155 ps: (csr_utils_pkg.sv:572) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0x4aba7c84) == 0x0
  UVM_INFO @ 10044924155 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:715) [aes_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 3.aes_stress_all_with_rand_reset.31870973620608293482967255218928305533036964128296797508398255807899122191814
    Line 309, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 133902001 ps: (cip_base_vseq.sv:715) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 133902001 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_fi_vseq.sv:69) virtual_sequencer [aes_fi_vseq] Was Able to finish without clearing reset has 1 failures:
- Test aes_fi has 1 failures.
  - 46.aes_fi.27173390978931005235032219129483337255227793079830627673469985010927378888771
    Line 19919, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/46.aes_fi/latest/run.log
```
  UVM_FATAL @  45839300 ps: (aes_fi_vseq.sv:69) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.aes_fi_vseq] Was Able to finish without clearing reset
  UVM_INFO @  45839300 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```