AES/MASKED Simulation Results

Wednesday February 21 2024 20:04:41 UTC

GitHub Revision: `df66f8a42e`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 105428938048998514387352931012238053576571450380985277214810281406530880002461

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	67.733us	1	1	100.00
V1	smoke	aes_smoke	14.000s	72.906us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	204.024us	5	5	100.00
V1	csr_rw	aes_csr_rw	4.000s	79.221us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	11.000s	3.341ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	247.799us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	5.000s	425.942us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	4.000s	79.221us	20	20	100.00
		aes_csr_aliasing	5.000s	247.799us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	14.000s	72.906us	50	50	100.00
		aes_config_error	26.000s	649.654us	50	50	100.00
		aes_stress	1.400m	2.786ms	50	50	100.00
V2	key_length	aes_smoke	14.000s	72.906us	50	50	100.00
		aes_config_error	26.000s	649.654us	50	50	100.00
		aes_stress	1.400m	2.786ms	50	50	100.00
V2	back2back	aes_stress	1.400m	2.786ms	50	50	100.00
		aes_b2b	31.000s	243.898us	50	50	100.00
V2	backpressure	aes_stress	1.400m	2.786ms	50	50	100.00
V2	multi_message	aes_smoke	14.000s	72.906us	50	50	100.00
		aes_config_error	26.000s	649.654us	50	50	100.00
		aes_stress	1.400m	2.786ms	50	50	100.00
		aes_alert_reset	1.900m	8.138ms	50	50	100.00
V2	failure_test	aes_man_cfg_err	9.000s	102.004us	50	50	100.00
		aes_config_error	26.000s	649.654us	50	50	100.00
		aes_alert_reset	1.900m	8.138ms	50	50	100.00
V2	trigger_clear_test	aes_clear	24.000s	654.458us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	22.000s	1.902ms	1	1	100.00
V2	reset_recovery	aes_alert_reset	1.900m	8.138ms	50	50	100.00
V2	stress	aes_stress	1.400m	2.786ms	50	50	100.00
V2	sideload	aes_stress	1.400m	2.786ms	50	50	100.00
		aes_sideload	13.000s	522.654us	50	50	100.00
V2	deinitialization	aes_deinit	24.000s	1.298ms	50	50	100.00
V2	stress_all	aes_stress_all	1.350m	1.915ms	9	10	90.00
V2	alert_test	aes_alert_test	13.000s	531.422us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	7.000s	276.501us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	7.000s	276.501us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	204.024us	5	5	100.00
		aes_csr_rw	4.000s	79.221us	20	20	100.00
		aes_csr_aliasing	5.000s	247.799us	5	5	100.00
		aes_same_csr_outstanding	6.000s	94.458us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	204.024us	5	5	100.00
		aes_csr_rw	4.000s	79.221us	20	20	100.00
		aes_csr_aliasing	5.000s	247.799us	5	5	100.00
		aes_same_csr_outstanding	6.000s	94.458us	20	20	100.00
V2		TOTAL			500	501	99.80
V2S	reseeding	aes_reseed	24.000s	746.647us	50	50	100.00
V2S	fault_inject	aes_fi	1.000m	2.303ms	50	50	100.00
		aes_control_fi	40.000s	10.212ms	279	300	93.00
		aes_cipher_fi	28.000s	10.010ms	340	350	97.14
V2S	shadow_reg_update_error	aes_shadow_reg_errors	5.000s	366.002us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	5.000s	366.002us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	5.000s	366.002us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	5.000s	366.002us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	5.000s	207.676us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	11.000s	1.554ms	5	5	100.00
		aes_tl_intg_err	14.000s	194.901us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	14.000s	194.901us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	1.900m	8.138ms	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	5.000s	366.002us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	14.000s	72.906us	50	50	100.00
		aes_stress	1.400m	2.786ms	50	50	100.00
		aes_alert_reset	1.900m	8.138ms	50	50	100.00
		aes_core_fi	31.000s	10.158ms	68	70	97.14
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	5.000s	366.002us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	9.000s	353.545us	50	50	100.00
		aes_stress	1.400m	2.786ms	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	1.400m	2.786ms	50	50	100.00
		aes_sideload	13.000s	522.654us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	9.000s	353.545us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	9.000s	353.545us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	9.000s	353.545us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	9.000s	353.545us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	9.000s	353.545us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	1.400m	2.786ms	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	1.400m	2.786ms	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	1.000m	2.303ms	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	1.000m	2.303ms	50	50	100.00
		aes_control_fi	40.000s	10.212ms	279	300	93.00
		aes_cipher_fi	28.000s	10.010ms	340	350	97.14
		aes_ctr_fi	9.000s	59.217us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	1.000m	2.303ms	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	1.000m	2.303ms	50	50	100.00
		aes_control_fi	40.000s	10.212ms	279	300	93.00
		aes_cipher_fi	28.000s	10.010ms	340	350	97.14
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	28.000s	10.010ms	340	350	97.14
V2S	sec_cm_ctr_fsm_sparse	aes_fi	1.000m	2.303ms	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	1.000m	2.303ms	50	50	100.00
		aes_control_fi	40.000s	10.212ms	279	300	93.00
		aes_ctr_fi	9.000s	59.217us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	1.000m	2.303ms	50	50	100.00
		aes_control_fi	40.000s	10.212ms	279	300	93.00
		aes_cipher_fi	28.000s	10.010ms	340	350	97.14
		aes_ctr_fi	9.000s	59.217us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	1.900m	8.138ms	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	1.000m	2.303ms	50	50	100.00
		aes_control_fi	40.000s	10.212ms	279	300	93.00
		aes_cipher_fi	28.000s	10.010ms	340	350	97.14
		aes_ctr_fi	9.000s	59.217us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	1.000m	2.303ms	50	50	100.00
		aes_control_fi	40.000s	10.212ms	279	300	93.00
		aes_cipher_fi	28.000s	10.010ms	340	350	97.14
		aes_ctr_fi	9.000s	59.217us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	1.000m	2.303ms	50	50	100.00
		aes_control_fi	40.000s	10.212ms	279	300	93.00
		aes_ctr_fi	9.000s	59.217us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	1.000m	2.303ms	50	50	100.00
		aes_control_fi	40.000s	10.212ms	279	300	93.00
		aes_cipher_fi	28.000s	10.010ms	340	350	97.14
V2S		TOTAL			952	985	96.65
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	2.317m	4.632ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1558	1602	97.25

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	12	92.31
V2S	11	11	8	72.73
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.55	98.92	97.29	99.42	95.75	97.72	97.78	99.11	97.41

Failure Buckets

Job aes_masked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 27 failures:
- Test aes_control_fi has 20 failures.
  - 3.aes_control_fi.34073240455901501676474085748994389940012297381454327887158856219609707759524
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/3.aes_control_fi/latest/run.log
```
  Job ID: smart:2ff23e26-1a4f-4b26-8822-4448a38f0540
```
  - 22.aes_control_fi.75103513790390561181830651258549818396387557342579784188716136480034463917001
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/22.aes_control_fi/latest/run.log
```
  Job ID: smart:3203049e-985a-46a3-b1a0-9a080f8471e2
```
  - ... and 18 more failures.
- Test aes_cipher_fi has 7 failures.
  - 34.aes_cipher_fi.70420488329232795764822885637103074593900691290628307051273591428155320522715
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/34.aes_cipher_fi/latest/run.log
```
  Job ID: smart:662b26ea-bdb3-4f9a-8739-bc68b04730d5
```
  - 73.aes_cipher_fi.52217896930850990165079356610508924742718157426035318790491199474256564006290
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/73.aes_cipher_fi/latest/run.log
```
  Job ID: smart:22b00af2-219b-4eed-804f-6776d07394fa
```
  - ... and 5 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 5 failures:

Test aes_stress_all_with_rand_reset has 5 failures.

3.aes_stress_all_with_rand_reset.69168109171295346767726351468048923623472166477563759039519674096229037052176
Line 675, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 4631586395 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 4631586395 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.aes_stress_all_with_rand_reset.99745810888793271785559512510928513255044701961913662206213041611243912577745
Line 1346, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/4.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2221064436 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 2221064436 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_FATAL (aes_reseed_vseq.sv:40) [aes_reseed_vseq] Check failed request_seen | finished_all_msgs == *'b* (* [*] vs * [*]) has 3 failures:
- Test aes_stress_all_with_rand_reset has 2 failures.
  - 2.aes_stress_all_with_rand_reset.86097334298637726257219572648180500536989125381397748874522200337037186909747
    Line 994, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 1553709623 ps: (aes_reseed_vseq.sv:40) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed request_seen | finished_all_msgs == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 1553709623 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 9.aes_stress_all_with_rand_reset.1481299038816876095694039949723127834960549941370468975524143290411740131488
    Line 722, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/9.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 1624463037 ps: (aes_reseed_vseq.sv:40) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed request_seen | finished_all_msgs == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 1624463037 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test aes_stress_all has 1 failures.
  - 8.aes_stress_all.90636731779924826798222601260144147967365001501520555218712097734529778484836
    Line 30571, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/8.aes_stress_all/latest/run.log
```
  UVM_FATAL @ 2440263302 ps: (aes_reseed_vseq.sv:40) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed request_seen | finished_all_msgs == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 2440263302 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 3 failures:
- Test aes_cipher_fi has 3 failures.
  - 27.aes_cipher_fi.57746467725563874397714626178630462067691978336179126244975314810760053837326
    Line 328, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/27.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10030608139 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10030608139 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 100.aes_cipher_fi.38303948726410952675065129678181466335915161896862472547108795692246329468872
    Line 328, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/100.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10019557207 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10019557207 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 2 failures:

Test aes_stress_all_with_rand_reset has 2 failures.

0.aes_stress_all_with_rand_reset.71405376945826498986935385352717690452349840260712398927372451663686212365841
Line 1098, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 938119804 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 938119804 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.101545543932878317315021351802482729343417741197960226954943957043577014525149
Line 1484, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1722417164 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1722417164 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_core_fi has 2 failures.
  - 6.aes_core_fi.43837382339381788557065374699568042117899410638802864909580281423431599585903
    Line 315, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/6.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10010059781 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10010059781 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 40.aes_core_fi.4636415961589586522733318201021713554254727180898035154058781778803257054818
    Line 317, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/40.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10157544302 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10157544302 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:775) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited too long to issue a reset with no outstanding accesses. has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 5.aes_stress_all_with_rand_reset.8519539431511868754206081231090861873552309941547986136170855206442975031560
    Line 380, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/5.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 429803040 ps: (cip_base_vseq.sv:775) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited too long to issue a reset with no outstanding accesses.
  UVM_INFO @ 429803040 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_control_fi has 1 failures.
  - 56.aes_control_fi.88266374353088474410747768613707095913489247744138747097827266448409563733238
    Line 321, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/56.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10211747849 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10211747849 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```