AES/MASKED Simulation Results

Sunday February 25 2024 20:02:21 UTC

GitHub Revision: `49a27e136c`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 17821327886248910358472250431024817182401150698618588470408418907520000067582

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	5.000s	329.805us	1	1	100.00
V1	smoke	aes_smoke	7.000s	154.803us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	13.000s	72.067us	5	5	100.00
V1	csr_rw	aes_csr_rw	8.000s	65.765us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	10.000s	1.888ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	8.000s	192.494us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	13.000s	79.736us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	8.000s	65.765us	20	20	100.00
		aes_csr_aliasing	8.000s	192.494us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	7.000s	154.803us	50	50	100.00
		aes_config_error	15.000s	508.348us	50	50	100.00
		aes_stress	37.000s	4.033ms	50	50	100.00
V2	key_length	aes_smoke	7.000s	154.803us	50	50	100.00
		aes_config_error	15.000s	508.348us	50	50	100.00
		aes_stress	37.000s	4.033ms	50	50	100.00
V2	back2back	aes_stress	37.000s	4.033ms	50	50	100.00
		aes_b2b	53.000s	698.671us	50	50	100.00
V2	backpressure	aes_stress	37.000s	4.033ms	50	50	100.00
V2	multi_message	aes_smoke	7.000s	154.803us	50	50	100.00
		aes_config_error	15.000s	508.348us	50	50	100.00
		aes_stress	37.000s	4.033ms	50	50	100.00
		aes_alert_reset	22.000s	688.973us	50	50	100.00
V2	failure_test	aes_man_cfg_err	6.000s	254.276us	50	50	100.00
		aes_config_error	15.000s	508.348us	50	50	100.00
		aes_alert_reset	22.000s	688.973us	50	50	100.00
V2	trigger_clear_test	aes_clear	46.517m	23.346ms	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	13.000s	1.144ms	1	1	100.00
V2	reset_recovery	aes_alert_reset	22.000s	688.973us	50	50	100.00
V2	stress	aes_stress	37.000s	4.033ms	50	50	100.00
V2	sideload	aes_stress	37.000s	4.033ms	50	50	100.00
		aes_sideload	9.000s	229.623us	50	50	100.00
V2	deinitialization	aes_deinit	8.000s	436.634us	50	50	100.00
V2	stress_all	aes_stress_all	1.767m	13.954ms	9	10	90.00
V2	alert_test	aes_alert_test	6.000s	64.574us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	8.000s	347.934us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	8.000s	347.934us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	13.000s	72.067us	5	5	100.00
		aes_csr_rw	8.000s	65.765us	20	20	100.00
		aes_csr_aliasing	8.000s	192.494us	5	5	100.00
		aes_same_csr_outstanding	14.000s	135.767us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	13.000s	72.067us	5	5	100.00
		aes_csr_rw	8.000s	65.765us	20	20	100.00
		aes_csr_aliasing	8.000s	192.494us	5	5	100.00
		aes_same_csr_outstanding	14.000s	135.767us	20	20	100.00
V2		TOTAL			500	501	99.80
V2S	reseeding	aes_reseed	51.000s	4.026ms	50	50	100.00
V2S	fault_inject	aes_fi	46.000s	3.205ms	50	50	100.00
		aes_control_fi	43.000s	10.129ms	278	300	92.67
		aes_cipher_fi	47.000s	10.013ms	337	350	96.29
V2S	shadow_reg_update_error	aes_shadow_reg_errors	15.000s	291.032us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	15.000s	291.032us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	15.000s	291.032us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	15.000s	291.032us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	9.000s	167.189us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	13.000s	1.990ms	5	5	100.00
		aes_tl_intg_err	14.000s	288.216us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	14.000s	288.216us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	22.000s	688.973us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	15.000s	291.032us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	7.000s	154.803us	50	50	100.00
		aes_stress	37.000s	4.033ms	50	50	100.00
		aes_alert_reset	22.000s	688.973us	50	50	100.00
		aes_core_fi	1.467m	10.031ms	68	70	97.14
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	15.000s	291.032us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	5.000s	248.680us	50	50	100.00
		aes_stress	37.000s	4.033ms	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	37.000s	4.033ms	50	50	100.00
		aes_sideload	9.000s	229.623us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	5.000s	248.680us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	5.000s	248.680us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	5.000s	248.680us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	5.000s	248.680us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	5.000s	248.680us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	37.000s	4.033ms	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	37.000s	4.033ms	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	46.000s	3.205ms	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	46.000s	3.205ms	50	50	100.00
		aes_control_fi	43.000s	10.129ms	278	300	92.67
		aes_cipher_fi	47.000s	10.013ms	337	350	96.29
		aes_ctr_fi	5.000s	265.378us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	46.000s	3.205ms	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	46.000s	3.205ms	50	50	100.00
		aes_control_fi	43.000s	10.129ms	278	300	92.67
		aes_cipher_fi	47.000s	10.013ms	337	350	96.29
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	47.000s	10.013ms	337	350	96.29
V2S	sec_cm_ctr_fsm_sparse	aes_fi	46.000s	3.205ms	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	46.000s	3.205ms	50	50	100.00
		aes_control_fi	43.000s	10.129ms	278	300	92.67
		aes_ctr_fi	5.000s	265.378us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	46.000s	3.205ms	50	50	100.00
		aes_control_fi	43.000s	10.129ms	278	300	92.67
		aes_cipher_fi	47.000s	10.013ms	337	350	96.29
		aes_ctr_fi	5.000s	265.378us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	22.000s	688.973us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	46.000s	3.205ms	50	50	100.00
		aes_control_fi	43.000s	10.129ms	278	300	92.67
		aes_cipher_fi	47.000s	10.013ms	337	350	96.29
		aes_ctr_fi	5.000s	265.378us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	46.000s	3.205ms	50	50	100.00
		aes_control_fi	43.000s	10.129ms	278	300	92.67
		aes_cipher_fi	47.000s	10.013ms	337	350	96.29
		aes_ctr_fi	5.000s	265.378us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	46.000s	3.205ms	50	50	100.00
		aes_control_fi	43.000s	10.129ms	278	300	92.67
		aes_ctr_fi	5.000s	265.378us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	46.000s	3.205ms	50	50	100.00
		aes_control_fi	43.000s	10.129ms	278	300	92.67
		aes_cipher_fi	47.000s	10.013ms	337	350	96.29
V2S		TOTAL			948	985	96.24
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	2.833m	7.724ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1554	1602	97.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	12	92.31
V2S	11	11	8	72.73
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.51	98.88	97.18	99.39	95.84	97.72	97.78	99.11	96.41

Failure Buckets

Job aes_masked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 22 failures:
- Test aes_cipher_fi has 7 failures.
  - 21.aes_cipher_fi.22142391351261776478113699728610859557413408533648447198785960701280851743639
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/21.aes_cipher_fi/latest/run.log
```
  Job ID: smart:7b427113-5c4d-4ef5-9f5d-ff932d34e43f
```
  - 34.aes_cipher_fi.44247521859729918864325872196723097296129939530137866730362498752916379105184
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/34.aes_cipher_fi/latest/run.log
```
  Job ID: smart:d4b8005e-c0d2-4a60-ac26-20ccafdae5af
```
  - ... and 5 more failures.
- Test aes_control_fi has 15 failures.
  - 26.aes_control_fi.92025424112994149154173792022816972316272617509185956834268657322480314190108
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/26.aes_control_fi/latest/run.log
```
  Job ID: smart:11015f70-8e6a-4ba6-891e-9f875ef586db
```
  - 39.aes_control_fi.74695465766210384974425500567776340656586466825885970615630538345350442493587
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/39.aes_control_fi/latest/run.log
```
  Job ID: smart:7a0f3b2d-cc23-47d3-a96c-1d7d8548e854
```
  - ... and 13 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 7 failures:
- Test aes_control_fi has 7 failures.
  - 6.aes_control_fi.46889066351671106542216519629885367436562520181987645133704753016066997711210
    Line 319, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/6.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10017420464 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10017420464 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 118.aes_control_fi.67697526423705099542916006755086796520009966852979843281030587022943801032995
    Line 324, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/118.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10105721407 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10105721407 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 6 failures:
- Test aes_cipher_fi has 6 failures.
  - 14.aes_cipher_fi.66848906042835846337009514962243852486293624836090624674815537032578338044495
    Line 329, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/14.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10044116508 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10044116508 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 173.aes_cipher_fi.16044427099060768580869098370502239221094172970977958975605132927316380699982
    Line 321, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/173.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10009359051 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10009359051 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 4 failures:

Test aes_stress_all_with_rand_reset has 4 failures.

0.aes_stress_all_with_rand_reset.18133445721130324107514429778590635405887571234304931338649016955641205211821
Line 633, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2120411178 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 2120411178 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.aes_stress_all_with_rand_reset.46312607369804133602881473404986823576420023656633463666532269815219538843258
Line 1241, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2489917343 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 2489917343 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 4 failures:

Test aes_stress_all_with_rand_reset has 4 failures.

3.aes_stress_all_with_rand_reset.68711983752099848707978487873566487874927151941065189712907633624294186080561
Line 871, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 3141372156 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 3141372156 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.aes_stress_all_with_rand_reset.29093201541771740114438862825856491080726697953062917270736081426134473936062
Line 642, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/4.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 188736460 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 188736460 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_ERROR (cip_base_vseq.sv:775) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited too long to issue a reset with no outstanding accesses. has 2 failures:
- Test aes_stress_all_with_rand_reset has 2 failures.
  - 1.aes_stress_all_with_rand_reset.60407913462719612517606975885539127610313644685262069769767470218453856992328
    Line 414, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 814474256 ps: (cip_base_vseq.sv:775) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited too long to issue a reset with no outstanding accesses.
  UVM_INFO @ 814474256 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 9.aes_stress_all_with_rand_reset.92055962223485453882321567761735894471664060341763568370109920660144859537335
    Line 1461, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/9.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 7724028330 ps: (cip_base_vseq.sv:775) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited too long to issue a reset with no outstanding accesses.
  UVM_INFO @ 7724028330 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_core_fi has 2 failures.
  - 7.aes_core_fi.64611868139114555543751670536597360387921845700971973599271353504463719142105
    Line 321, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/7.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10058429044 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10058429044 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 37.aes_core_fi.64444421575543396170402233504946644094886294891673138938449750209471153218931
    Line 327, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/37.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10030699394 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10030699394 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,978): Assertion AesSecCmDataRegLocalEscDataOut has failed (* cycles, starting * PS) has 1 failures:
- Test aes_stress_all has 1 failures.
  - 6.aes_stress_all.56530114673761848288679998007107048137344886871642457791084325671077058731205
    Line 49680, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/6.aes_stress_all/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,978): (time 1114485644 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 1114464811 PS)
  UVM_ERROR @ 1114485644 ps: (aes_core.sv:978) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut
  UVM_INFO @ 1114485644 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```