AES/MASKED Simulation Results

Wednesday February 28 2024 23:53:28 UTC

GitHub Revision: `32ed2c4230`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 10708067410766204292161266966839433462058030635847883045650346145926493105783

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	4.000s	76.820us	1	1	100.00
V1	smoke	aes_smoke	49.000s	1.734ms	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	72.270us	5	5	100.00
V1	csr_rw	aes_csr_rw	8.000s	59.082us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	11.000s	839.378us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	8.000s	105.582us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	4.000s	73.263us	19	20	95.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	8.000s	59.082us	20	20	100.00
		aes_csr_aliasing	8.000s	105.582us	5	5	100.00
V1		TOTAL			105	106	99.06
V2	algorithm	aes_smoke	49.000s	1.734ms	50	50	100.00
		aes_config_error	22.000s	639.842us	50	50	100.00
		aes_stress	9.000s	410.095us	50	50	100.00
V2	key_length	aes_smoke	49.000s	1.734ms	50	50	100.00
		aes_config_error	22.000s	639.842us	50	50	100.00
		aes_stress	9.000s	410.095us	50	50	100.00
V2	back2back	aes_stress	9.000s	410.095us	50	50	100.00
		aes_b2b	1.000m	700.646us	50	50	100.00
V2	backpressure	aes_stress	9.000s	410.095us	50	50	100.00
V2	multi_message	aes_smoke	49.000s	1.734ms	50	50	100.00
		aes_config_error	22.000s	639.842us	50	50	100.00
		aes_stress	9.000s	410.095us	50	50	100.00
		aes_alert_reset	34.000s	1.278ms	50	50	100.00
V2	failure_test	aes_man_cfg_err	13.000s	762.970us	50	50	100.00
		aes_config_error	22.000s	639.842us	50	50	100.00
		aes_alert_reset	34.000s	1.278ms	50	50	100.00
V2	trigger_clear_test	aes_clear	53.000s	1.698ms	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	15.000s	827.537us	1	1	100.00
V2	reset_recovery	aes_alert_reset	34.000s	1.278ms	50	50	100.00
V2	stress	aes_stress	9.000s	410.095us	50	50	100.00
V2	sideload	aes_stress	9.000s	410.095us	50	50	100.00
		aes_sideload	1.250m	2.574ms	50	50	100.00
V2	deinitialization	aes_deinit	12.000s	188.070us	50	50	100.00
V2	stress_all	aes_stress_all	1.450m	4.680ms	10	10	100.00
V2	alert_test	aes_alert_test	5.000s	122.022us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	9.000s	128.899us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	9.000s	128.899us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	72.270us	5	5	100.00
		aes_csr_rw	8.000s	59.082us	20	20	100.00
		aes_csr_aliasing	8.000s	105.582us	5	5	100.00
		aes_same_csr_outstanding	14.000s	73.035us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	72.270us	5	5	100.00
		aes_csr_rw	8.000s	59.082us	20	20	100.00
		aes_csr_aliasing	8.000s	105.582us	5	5	100.00
		aes_same_csr_outstanding	14.000s	73.035us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	26.000s	1.356ms	50	50	100.00
V2S	fault_inject	aes_fi	15.000s	592.420us	50	50	100.00
		aes_control_fi	49.000s	10.012ms	282	300	94.00
		aes_cipher_fi	51.000s	10.011ms	339	350	96.86
V2S	shadow_reg_update_error	aes_shadow_reg_errors	8.000s	67.942us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	8.000s	67.942us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	8.000s	67.942us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	8.000s	67.942us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	1.733m	10.049ms	19	20	95.00
V2S	tl_intg_err	aes_sec_cm	8.000s	1.274ms	5	5	100.00
		aes_tl_intg_err	10.000s	218.638us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	10.000s	218.638us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	34.000s	1.278ms	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	8.000s	67.942us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	49.000s	1.734ms	50	50	100.00
		aes_stress	9.000s	410.095us	50	50	100.00
		aes_alert_reset	34.000s	1.278ms	50	50	100.00
		aes_core_fi	1.233m	10.139ms	67	70	95.71
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	8.000s	67.942us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	5.000s	123.829us	50	50	100.00
		aes_stress	9.000s	410.095us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	9.000s	410.095us	50	50	100.00
		aes_sideload	1.250m	2.574ms	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	5.000s	123.829us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	5.000s	123.829us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	5.000s	123.829us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	5.000s	123.829us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	5.000s	123.829us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	9.000s	410.095us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	9.000s	410.095us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	15.000s	592.420us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	15.000s	592.420us	50	50	100.00
		aes_control_fi	49.000s	10.012ms	282	300	94.00
		aes_cipher_fi	51.000s	10.011ms	339	350	96.86
		aes_ctr_fi	4.000s	104.672us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	15.000s	592.420us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	15.000s	592.420us	50	50	100.00
		aes_control_fi	49.000s	10.012ms	282	300	94.00
		aes_cipher_fi	51.000s	10.011ms	339	350	96.86
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	51.000s	10.011ms	339	350	96.86
V2S	sec_cm_ctr_fsm_sparse	aes_fi	15.000s	592.420us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	15.000s	592.420us	50	50	100.00
		aes_control_fi	49.000s	10.012ms	282	300	94.00
		aes_ctr_fi	4.000s	104.672us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	15.000s	592.420us	50	50	100.00
		aes_control_fi	49.000s	10.012ms	282	300	94.00
		aes_cipher_fi	51.000s	10.011ms	339	350	96.86
		aes_ctr_fi	4.000s	104.672us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	34.000s	1.278ms	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	15.000s	592.420us	50	50	100.00
		aes_control_fi	49.000s	10.012ms	282	300	94.00
		aes_cipher_fi	51.000s	10.011ms	339	350	96.86
		aes_ctr_fi	4.000s	104.672us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	15.000s	592.420us	50	50	100.00
		aes_control_fi	49.000s	10.012ms	282	300	94.00
		aes_cipher_fi	51.000s	10.011ms	339	350	96.86
		aes_ctr_fi	4.000s	104.672us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	15.000s	592.420us	50	50	100.00
		aes_control_fi	49.000s	10.012ms	282	300	94.00
		aes_ctr_fi	4.000s	104.672us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	15.000s	592.420us	50	50	100.00
		aes_control_fi	49.000s	10.012ms	282	300	94.00
		aes_cipher_fi	51.000s	10.011ms	339	350	96.86
V2S		TOTAL			952	985	96.65
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	53.000s	2.608ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1558	1602	97.25

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	6	85.71
V2	13	13	13	100.00
V2S	11	11	7	63.64
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.53	98.92	97.29	99.42	95.79	97.64	97.78	98.96	96.41

Failure Buckets

Job aes_masked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 20 failures:
- Test aes_control_fi has 14 failures.
  - 6.aes_control_fi.28006424065293068514122921318460118845126605612811485133550376825139447579765
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/6.aes_control_fi/latest/run.log
```
  Job ID: smart:4ec5a0c4-ae4c-4dcb-a805-836c681d584d
```
  - 19.aes_control_fi.83961847351219130720873649243513705490621378549314772332707422126161421806597
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/19.aes_control_fi/latest/run.log
```
  Job ID: smart:9699f64b-a3f5-4810-b059-9270ac5a1157
```
  - ... and 12 more failures.
- Test aes_cipher_fi has 6 failures.
  - 36.aes_cipher_fi.1497948457562897916938371072179770029714360365182179556926067261174969784813
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/36.aes_cipher_fi/latest/run.log
```
  Job ID: smart:aa99f254-87e8-4eb0-9de4-11fb1517c3a4
```
  - 55.aes_cipher_fi.77775017797437253252931523055036349209673357926397406652941367122640838308916
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/55.aes_cipher_fi/latest/run.log
```
  Job ID: smart:35182767-c9e3-4dec-baf1-1d7659a2cec0
```
  - ... and 4 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 6 failures:

Test aes_stress_all_with_rand_reset has 6 failures.

0.aes_stress_all_with_rand_reset.80537984759492002114045169055616373556099026414155908744543349089860167067553
Line 539, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 332186697 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 332186697 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.60716366824806573123096428080900962248364632436336277768699558909269546193686
Line 523, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 4092434082 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 4092434082 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 5 failures:
- Test aes_cipher_fi has 5 failures.
  - 74.aes_cipher_fi.22999109347562716852169824286510866271091860806879605918889214631296815652657
    Line 327, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/74.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10011194748 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10011194748 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 81.aes_cipher_fi.51187906152158919365219479002956409961992082631529397836611833880587953779985
    Line 315, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/81.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10009414179 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10009414179 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 4 failures:
- Test aes_control_fi has 4 failures.
  - 10.aes_control_fi.30015208400579436687625743430522345035964994160719276184602466133070321975809
    Line 315, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/10.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10011698609 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10011698609 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 123.aes_control_fi.6584785994744386842971225570880003263675567088180248989740719413131101855448
    Line 327, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/123.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10005480377 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10005480377 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 3 failures:

Test aes_stress_all_with_rand_reset has 3 failures.

3.aes_stress_all_with_rand_reset.41699156979149622166753163781892534861660896207744119669474574735776487422007
Line 1286, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2608419515 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 2608419515 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.aes_stress_all_with_rand_reset.66199830500456196205890761260576845693981447029355117403588709134550950932492
Line 917, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/4.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 3549076438 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 3549076438 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 3 failures:
- Test aes_core_fi has 3 failures.
  - 25.aes_core_fi.32006413596422301310560891136305694235430598476581986389979685868853728211164
    Line 323, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/25.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10060464933 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10060464933 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 30.aes_core_fi.86556867830214732673150118951201571821658470043278940035834625528606797483966
    Line 317, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/30.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10009929713 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10009929713 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL (csr_utils_pkg.sv:572) [csr_utils::csr_spinwait] timeout aes_reg_block.status.output_valid (addr=*) == * has 1 failures:
- Test aes_shadow_reg_errors_with_csr_rw has 1 failures.
  - 5.aes_shadow_reg_errors_with_csr_rw.30745275532602056809371880961696381416272804196344763445749257848326466310305
    Line 288, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/5.aes_shadow_reg_errors_with_csr_rw/latest/run.log
```
  UVM_FATAL @ 10048695522 ps: (csr_utils_pkg.sv:572) [csr_utils::csr_spinwait] timeout aes_reg_block.status.output_valid (addr=0x3cffee84) == 0x0
  UVM_INFO @ 10048695522 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:789) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 6.aes_stress_all_with_rand_reset.99976799622445012357053590826673302287070365406720441843061366898548853300142
    Line 374, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/6.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 435533178 ps: (cip_base_vseq.sv:789) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 435533178 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:789) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test aes_csr_mem_rw_with_rand_reset has 1 failures.
  - 19.aes_csr_mem_rw_with_rand_reset.87696272774827604555758926242613813868899170315114949961251136888715907298876
    Line 285, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/19.aes_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 111661020 ps: (cip_base_vseq.sv:789) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 111661020 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```