AES/MASKED Simulation Results

Saturday June 29 2024 23:02:35 UTC

GitHub Revision: b33f0bcb4a

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 9407974028806500767465982655187958599819354731549473124644158596869486113221

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 wake_up aes_wake_up 4.000s 99.107us 1 1 100.00
V1 smoke aes_smoke 16.000s 458.834us 50 50 100.00
V1 csr_hw_reset aes_csr_hw_reset 5.000s 65.440us 5 5 100.00
V1 csr_rw aes_csr_rw 5.000s 105.215us 20 20 100.00
V1 csr_bit_bash aes_csr_bit_bash 16.000s 15.818ms 5 5 100.00
V1 csr_aliasing aes_csr_aliasing 5.000s 303.815us 5 5 100.00
V1 csr_mem_rw_with_rand_reset aes_csr_mem_rw_with_rand_reset 8.000s 81.224us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr aes_csr_rw 5.000s 105.215us 20 20 100.00
aes_csr_aliasing 5.000s 303.815us 5 5 100.00
V1 TOTAL 106 106 100.00
V2 algorithm aes_smoke 16.000s 458.834us 50 50 100.00
aes_config_error 17.000s 508.135us 50 50 100.00
aes_stress 38.000s 1.062ms 50 50 100.00
V2 key_length aes_smoke 16.000s 458.834us 50 50 100.00
aes_config_error 17.000s 508.135us 50 50 100.00
aes_stress 38.000s 1.062ms 50 50 100.00
V2 back2back aes_stress 38.000s 1.062ms 50 50 100.00
aes_b2b 1.333m 839.895us 50 50 100.00
V2 backpressure aes_stress 38.000s 1.062ms 50 50 100.00
V2 multi_message aes_smoke 16.000s 458.834us 50 50 100.00
aes_config_error 17.000s 508.135us 50 50 100.00
aes_stress 38.000s 1.062ms 50 50 100.00
aes_alert_reset 28.000s 843.715us 50 50 100.00
V2 failure_test aes_man_cfg_err 11.000s 367.357us 50 50 100.00
aes_config_error 17.000s 508.135us 50 50 100.00
aes_alert_reset 28.000s 843.715us 50 50 100.00
V2 trigger_clear_test aes_clear 14.000s 588.574us 50 50 100.00
V2 nist_test_vectors aes_nist_vectors 11.000s 1.071ms 1 1 100.00
V2 reset_recovery aes_alert_reset 28.000s 843.715us 50 50 100.00
V2 stress aes_stress 38.000s 1.062ms 50 50 100.00
V2 sideload aes_stress 38.000s 1.062ms 50 50 100.00
aes_sideload 14.000s 674.840us 50 50 100.00
V2 deinitialization aes_deinit 22.000s 1.257ms 50 50 100.00
V2 stress_all aes_stress_all 1.350m 2.711ms 10 10 100.00
V2 alert_test aes_alert_test 6.000s 232.196us 50 50 100.00
V2 tl_d_oob_addr_access aes_tl_errors 15.000s 125.367us 20 20 100.00
V2 tl_d_illegal_access aes_tl_errors 15.000s 125.367us 20 20 100.00
V2 tl_d_outstanding_access aes_csr_hw_reset 5.000s 65.440us 5 5 100.00
aes_csr_rw 5.000s 105.215us 20 20 100.00
aes_csr_aliasing 5.000s 303.815us 5 5 100.00
aes_same_csr_outstanding 4.000s 240.242us 20 20 100.00
V2 tl_d_partial_access aes_csr_hw_reset 5.000s 65.440us 5 5 100.00
aes_csr_rw 5.000s 105.215us 20 20 100.00
aes_csr_aliasing 5.000s 303.815us 5 5 100.00
aes_same_csr_outstanding 4.000s 240.242us 20 20 100.00
V2 TOTAL 501 501 100.00
V2S reseeding aes_reseed 1.367m 2.652ms 49 50 98.00
V2S fault_inject aes_fi 1.533m 4.061ms 50 50 100.00
aes_control_fi 52.000s 10.009ms 279 300 93.00
aes_cipher_fi 46.000s 10.067ms 339 350 96.86
V2S shadow_reg_update_error aes_shadow_reg_errors 4.000s 70.084us 20 20 100.00
V2S shadow_reg_read_clear_staged_value aes_shadow_reg_errors 4.000s 70.084us 20 20 100.00
V2S shadow_reg_storage_error aes_shadow_reg_errors 4.000s 70.084us 20 20 100.00
V2S shadowed_reset_glitch aes_shadow_reg_errors 4.000s 70.084us 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw aes_shadow_reg_errors_with_csr_rw 4.000s 151.475us 20 20 100.00
V2S tl_intg_err aes_sec_cm 11.000s 822.697us 5 5 100.00
aes_tl_intg_err 6.000s 2.258ms 20 20 100.00
V2S sec_cm_bus_integrity aes_tl_intg_err 6.000s 2.258ms 20 20 100.00
V2S sec_cm_lc_escalate_en_intersig_mubi aes_alert_reset 28.000s 843.715us 50 50 100.00
V2S sec_cm_main_config_shadow aes_shadow_reg_errors 4.000s 70.084us 20 20 100.00
V2S sec_cm_main_config_sparse aes_smoke 16.000s 458.834us 50 50 100.00
aes_stress 38.000s 1.062ms 50 50 100.00
aes_alert_reset 28.000s 843.715us 50 50 100.00
aes_core_fi 25.000s 3.023ms 69 70 98.57
V2S sec_cm_aux_config_shadow aes_shadow_reg_errors 4.000s 70.084us 20 20 100.00
V2S sec_cm_aux_config_regwen aes_readability 4.000s 75.236us 50 50 100.00
aes_stress 38.000s 1.062ms 50 50 100.00
V2S sec_cm_key_sideload aes_stress 38.000s 1.062ms 50 50 100.00
aes_sideload 14.000s 674.840us 50 50 100.00
V2S sec_cm_key_sw_unreadable aes_readability 4.000s 75.236us 50 50 100.00
V2S sec_cm_data_reg_sw_unreadable aes_readability 4.000s 75.236us 50 50 100.00
V2S sec_cm_key_sec_wipe aes_readability 4.000s 75.236us 50 50 100.00
V2S sec_cm_iv_config_sec_wipe aes_readability 4.000s 75.236us 50 50 100.00
V2S sec_cm_data_reg_sec_wipe aes_readability 4.000s 75.236us 50 50 100.00
V2S sec_cm_data_reg_key_sca aes_stress 38.000s 1.062ms 50 50 100.00
V2S sec_cm_key_masking aes_stress 38.000s 1.062ms 50 50 100.00
V2S sec_cm_main_fsm_sparse aes_fi 1.533m 4.061ms 50 50 100.00
V2S sec_cm_main_fsm_redun aes_fi 1.533m 4.061ms 50 50 100.00
aes_control_fi 52.000s 10.009ms 279 300 93.00
aes_cipher_fi 46.000s 10.067ms 339 350 96.86
aes_ctr_fi 4.000s 103.630us 50 50 100.00
V2S sec_cm_cipher_fsm_sparse aes_fi 1.533m 4.061ms 50 50 100.00
V2S sec_cm_cipher_fsm_redun aes_fi 1.533m 4.061ms 50 50 100.00
aes_control_fi 52.000s 10.009ms 279 300 93.00
aes_cipher_fi 46.000s 10.067ms 339 350 96.86
V2S sec_cm_cipher_ctr_redun aes_cipher_fi 46.000s 10.067ms 339 350 96.86
V2S sec_cm_ctr_fsm_sparse aes_fi 1.533m 4.061ms 50 50 100.00
V2S sec_cm_ctr_fsm_redun aes_fi 1.533m 4.061ms 50 50 100.00
aes_control_fi 52.000s 10.009ms 279 300 93.00
aes_ctr_fi 4.000s 103.630us 50 50 100.00
V2S sec_cm_ctrl_sparse aes_fi 1.533m 4.061ms 50 50 100.00
aes_control_fi 52.000s 10.009ms 279 300 93.00
aes_cipher_fi 46.000s 10.067ms 339 350 96.86
aes_ctr_fi 4.000s 103.630us 50 50 100.00
V2S sec_cm_main_fsm_global_esc aes_alert_reset 28.000s 843.715us 50 50 100.00
V2S sec_cm_main_fsm_local_esc aes_fi 1.533m 4.061ms 50 50 100.00
aes_control_fi 52.000s 10.009ms 279 300 93.00
aes_cipher_fi 46.000s 10.067ms 339 350 96.86
aes_ctr_fi 4.000s 103.630us 50 50 100.00
V2S sec_cm_cipher_fsm_local_esc aes_fi 1.533m 4.061ms 50 50 100.00
aes_control_fi 52.000s 10.009ms 279 300 93.00
aes_cipher_fi 46.000s 10.067ms 339 350 96.86
aes_ctr_fi 4.000s 103.630us 50 50 100.00
V2S sec_cm_ctr_fsm_local_esc aes_fi 1.533m 4.061ms 50 50 100.00
aes_control_fi 52.000s 10.009ms 279 300 93.00
aes_ctr_fi 4.000s 103.630us 50 50 100.00
V2S sec_cm_data_reg_local_esc aes_fi 1.533m 4.061ms 50 50 100.00
aes_control_fi 52.000s 10.009ms 279 300 93.00
aes_cipher_fi 46.000s 10.067ms 339 350 96.86
V2S TOTAL 951 985 96.55
V3 stress_all_with_rand_reset aes_stress_all_with_rand_reset 5.017m 17.888ms 0 10 0.00
V3 TOTAL 0 10 0.00
TOTAL 1558 1602 97.25

Testplan Progress

Items Total Written Passing Progress
V1 7 7 7 100.00
V2 13 13 13 100.00
V2S 11 11 7 63.64
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
98.37 98.55 96.32 99.45 95.72 97.72 100.00 99.11 97.21

Failure Buckets

Past Results