AES/MASKED Simulation Results

Saturday June 29 2024 23:02:35 UTC

GitHub Revision: `b33f0bcb4a`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 9407974028806500767465982655187958599819354731549473124644158596869486113221

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	4.000s	99.107us	1	1	100.00
V1	smoke	aes_smoke	16.000s	458.834us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	5.000s	65.440us	5	5	100.00
V1	csr_rw	aes_csr_rw	5.000s	105.215us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	16.000s	15.818ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	303.815us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	8.000s	81.224us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	5.000s	105.215us	20	20	100.00
		aes_csr_aliasing	5.000s	303.815us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	16.000s	458.834us	50	50	100.00
		aes_config_error	17.000s	508.135us	50	50	100.00
		aes_stress	38.000s	1.062ms	50	50	100.00
V2	key_length	aes_smoke	16.000s	458.834us	50	50	100.00
		aes_config_error	17.000s	508.135us	50	50	100.00
		aes_stress	38.000s	1.062ms	50	50	100.00
V2	back2back	aes_stress	38.000s	1.062ms	50	50	100.00
		aes_b2b	1.333m	839.895us	50	50	100.00
V2	backpressure	aes_stress	38.000s	1.062ms	50	50	100.00
V2	multi_message	aes_smoke	16.000s	458.834us	50	50	100.00
		aes_config_error	17.000s	508.135us	50	50	100.00
		aes_stress	38.000s	1.062ms	50	50	100.00
		aes_alert_reset	28.000s	843.715us	50	50	100.00
V2	failure_test	aes_man_cfg_err	11.000s	367.357us	50	50	100.00
		aes_config_error	17.000s	508.135us	50	50	100.00
		aes_alert_reset	28.000s	843.715us	50	50	100.00
V2	trigger_clear_test	aes_clear	14.000s	588.574us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	11.000s	1.071ms	1	1	100.00
V2	reset_recovery	aes_alert_reset	28.000s	843.715us	50	50	100.00
V2	stress	aes_stress	38.000s	1.062ms	50	50	100.00
V2	sideload	aes_stress	38.000s	1.062ms	50	50	100.00
		aes_sideload	14.000s	674.840us	50	50	100.00
V2	deinitialization	aes_deinit	22.000s	1.257ms	50	50	100.00
V2	stress_all	aes_stress_all	1.350m	2.711ms	10	10	100.00
V2	alert_test	aes_alert_test	6.000s	232.196us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	15.000s	125.367us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	15.000s	125.367us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	5.000s	65.440us	5	5	100.00
		aes_csr_rw	5.000s	105.215us	20	20	100.00
		aes_csr_aliasing	5.000s	303.815us	5	5	100.00
		aes_same_csr_outstanding	4.000s	240.242us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	5.000s	65.440us	5	5	100.00
		aes_csr_rw	5.000s	105.215us	20	20	100.00
		aes_csr_aliasing	5.000s	303.815us	5	5	100.00
		aes_same_csr_outstanding	4.000s	240.242us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	1.367m	2.652ms	49	50	98.00
V2S	fault_inject	aes_fi	1.533m	4.061ms	50	50	100.00
		aes_control_fi	52.000s	10.009ms	279	300	93.00
		aes_cipher_fi	46.000s	10.067ms	339	350	96.86
V2S	shadow_reg_update_error	aes_shadow_reg_errors	4.000s	70.084us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	4.000s	70.084us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	4.000s	70.084us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	4.000s	70.084us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	4.000s	151.475us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	11.000s	822.697us	5	5	100.00
		aes_tl_intg_err	6.000s	2.258ms	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	6.000s	2.258ms	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	28.000s	843.715us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	4.000s	70.084us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	16.000s	458.834us	50	50	100.00
		aes_stress	38.000s	1.062ms	50	50	100.00
		aes_alert_reset	28.000s	843.715us	50	50	100.00
		aes_core_fi	25.000s	3.023ms	69	70	98.57
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	4.000s	70.084us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	4.000s	75.236us	50	50	100.00
		aes_stress	38.000s	1.062ms	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	38.000s	1.062ms	50	50	100.00
		aes_sideload	14.000s	674.840us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	4.000s	75.236us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	4.000s	75.236us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	4.000s	75.236us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	4.000s	75.236us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	4.000s	75.236us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	38.000s	1.062ms	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	38.000s	1.062ms	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	1.533m	4.061ms	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	1.533m	4.061ms	50	50	100.00
		aes_control_fi	52.000s	10.009ms	279	300	93.00
		aes_cipher_fi	46.000s	10.067ms	339	350	96.86
		aes_ctr_fi	4.000s	103.630us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	1.533m	4.061ms	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	1.533m	4.061ms	50	50	100.00
		aes_control_fi	52.000s	10.009ms	279	300	93.00
		aes_cipher_fi	46.000s	10.067ms	339	350	96.86
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	46.000s	10.067ms	339	350	96.86
V2S	sec_cm_ctr_fsm_sparse	aes_fi	1.533m	4.061ms	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	1.533m	4.061ms	50	50	100.00
		aes_control_fi	52.000s	10.009ms	279	300	93.00
		aes_ctr_fi	4.000s	103.630us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	1.533m	4.061ms	50	50	100.00
		aes_control_fi	52.000s	10.009ms	279	300	93.00
		aes_cipher_fi	46.000s	10.067ms	339	350	96.86
		aes_ctr_fi	4.000s	103.630us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	28.000s	843.715us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	1.533m	4.061ms	50	50	100.00
		aes_control_fi	52.000s	10.009ms	279	300	93.00
		aes_cipher_fi	46.000s	10.067ms	339	350	96.86
		aes_ctr_fi	4.000s	103.630us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	1.533m	4.061ms	50	50	100.00
		aes_control_fi	52.000s	10.009ms	279	300	93.00
		aes_cipher_fi	46.000s	10.067ms	339	350	96.86
		aes_ctr_fi	4.000s	103.630us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	1.533m	4.061ms	50	50	100.00
		aes_control_fi	52.000s	10.009ms	279	300	93.00
		aes_ctr_fi	4.000s	103.630us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	1.533m	4.061ms	50	50	100.00
		aes_control_fi	52.000s	10.009ms	279	300	93.00
		aes_cipher_fi	46.000s	10.067ms	339	350	96.86
V2S		TOTAL			951	985	96.55
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	5.017m	17.888ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1558	1602	97.25

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	13	100.00
V2S	11	11	7	63.64
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.37	98.55	96.32	99.45	95.72	97.72	100.00	99.11	97.21

Failure Buckets

Job aes_masked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 21 failures:
- Test aes_control_fi has 16 failures.
  - 0.aes_control_fi.9328979984466686532988250405781228961522206853752351036565308774937127140762
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_control_fi/latest/run.log
```
  Job ID: smart:ed00f130-32d4-4ad4-863c-6c18c04312d9
```
  - 34.aes_control_fi.28699823551265804714931210876080133542499308251372830191262141109562239431596
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/34.aes_control_fi/latest/run.log
```
  Job ID: smart:b1f1473a-8b43-467c-9e9e-43835da5105a
```
  - ... and 14 more failures.
- Test aes_cipher_fi has 5 failures.
  - 23.aes_cipher_fi.108408235047248124853734434625784610832579187579366093768958706222695187657631
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/23.aes_cipher_fi/latest/run.log
```
  Job ID: smart:01b01c3a-4699-4815-822c-c8d620406660
```
  - 107.aes_cipher_fi.52317290956058284774784530576384347919118226757267032021336814093552278665860
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/107.aes_cipher_fi/latest/run.log
```
  Job ID: smart:dfd23297-4ff6-4956-bbae-4293e4c3c2b5
```
  - ... and 3 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 6 failures:

Test aes_stress_all_with_rand_reset has 6 failures.

0.aes_stress_all_with_rand_reset.109568937697219163412428526524455882884728903785535151217795102914309328462214
Line 832, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 17887743839 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 17887743839 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.15302381830097611699961670923512997384540217118600324570141909788667346231350
Line 945, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2348373361 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 2348373361 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 6 failures:
- Test aes_cipher_fi has 6 failures.
  - 48.aes_cipher_fi.1814198331813000407222691554092386447577488967560406283417617915046315019580
    Line 319, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/48.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10058958768 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10058958768 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 96.aes_cipher_fi.110085883794513155929139092111520660988569704037363780591192982834902848435358
    Line 315, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/96.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10066521046 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10066521046 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 5 failures:
- Test aes_control_fi has 5 failures.
  - 39.aes_control_fi.83011183634500888350973686424415181766140374970462169671486714278037568636802
    Line 314, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/39.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10016253607 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10016253607 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 51.aes_control_fi.38858478657755245553461150072921875716063018973133121464635542026345640921270
    Line 332, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/51.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10008604572 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10008604572 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 3 failures:

Test aes_stress_all_with_rand_reset has 3 failures.

3.aes_stress_all_with_rand_reset.100235604054743930516670140316367032949587737878590609305382135531612901687071
Line 1418, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 747281426 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 747281426 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.aes_stress_all_with_rand_reset.22837871584419407203587522218939183711565281093694757695726903959655386656930
Line 1110, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/4.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 552021391 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 552021391 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,987): Assertion AesSecCmDataRegLocalEscDataOut has failed (* cycles, starting * PS) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 2.aes_stress_all_with_rand_reset.277876703002419200591886401107020335210785740093738361262348391925814195375
    Line 701, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,987): (time 3177582408 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 3177559152 PS)
  UVM_ERROR @ 3177582408 ps: (aes_core.sv:987) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut
  UVM_INFO @ 3177582408 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 8.aes_core_fi.4537273990196405738678967178516617941054202622418409773754611882585819265131
    Line 320, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/8.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10015432912 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10015432912 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (aes_reseed_vseq.sv:40) [aes_reseed_vseq] Check failed request_seen | finished_all_msgs == *'b* (* [*] vs * [*]) has 1 failures:
- Test aes_reseed has 1 failures.
  - 44.aes_reseed.53283172443353880166374146870737433516554295038717376675309949051915212427179
    Line 984, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/44.aes_reseed/latest/run.log
```
  UVM_FATAL @  94711848 ps: (aes_reseed_vseq.sv:40) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed request_seen | finished_all_msgs == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @  94711848 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```