AES/MASKED Simulation Results

Wednesday June 26 2024 23:02:36 UTC

GitHub Revision: `be1c4a4f52`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 44766564427213563291105655232733134394512207819884794315335669279596867428010

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	4.000s	58.452us	1	1	100.00
V1	smoke	aes_smoke	11.000s	483.430us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	58.876us	5	5	100.00
V1	csr_rw	aes_csr_rw	4.000s	208.189us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	12.000s	1.384ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	581.813us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	3.000s	110.804us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	4.000s	208.189us	20	20	100.00
		aes_csr_aliasing	5.000s	581.813us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	11.000s	483.430us	50	50	100.00
		aes_config_error	21.000s	2.976ms	50	50	100.00
		aes_stress	18.000s	483.632us	50	50	100.00
V2	key_length	aes_smoke	11.000s	483.430us	50	50	100.00
		aes_config_error	21.000s	2.976ms	50	50	100.00
		aes_stress	18.000s	483.632us	50	50	100.00
V2	back2back	aes_stress	18.000s	483.632us	50	50	100.00
		aes_b2b	1.083m	754.951us	50	50	100.00
V2	backpressure	aes_stress	18.000s	483.632us	50	50	100.00
V2	multi_message	aes_smoke	11.000s	483.430us	50	50	100.00
		aes_config_error	21.000s	2.976ms	50	50	100.00
		aes_stress	18.000s	483.632us	50	50	100.00
		aes_alert_reset	21.000s	1.395ms	50	50	100.00
V2	failure_test	aes_man_cfg_err	4.000s	58.069us	50	50	100.00
		aes_config_error	21.000s	2.976ms	50	50	100.00
		aes_alert_reset	21.000s	1.395ms	50	50	100.00
V2	trigger_clear_test	aes_clear	1.650m	3.458ms	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	11.000s	575.719us	1	1	100.00
V2	reset_recovery	aes_alert_reset	21.000s	1.395ms	50	50	100.00
V2	stress	aes_stress	18.000s	483.632us	50	50	100.00
V2	sideload	aes_stress	18.000s	483.632us	50	50	100.00
		aes_sideload	47.000s	1.533ms	50	50	100.00
V2	deinitialization	aes_deinit	27.000s	8.517ms	50	50	100.00
V2	stress_all	aes_stress_all	1.500m	1.727ms	10	10	100.00
V2	alert_test	aes_alert_test	8.000s	69.585us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	6.000s	727.932us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	6.000s	727.932us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	58.876us	5	5	100.00
		aes_csr_rw	4.000s	208.189us	20	20	100.00
		aes_csr_aliasing	5.000s	581.813us	5	5	100.00
		aes_same_csr_outstanding	4.000s	302.202us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	58.876us	5	5	100.00
		aes_csr_rw	4.000s	208.189us	20	20	100.00
		aes_csr_aliasing	5.000s	581.813us	5	5	100.00
		aes_same_csr_outstanding	4.000s	302.202us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	54.000s	1.498ms	50	50	100.00
V2S	fault_inject	aes_fi	24.000s	1.646ms	50	50	100.00
		aes_control_fi	50.000s	10.008ms	270	300	90.00
		aes_cipher_fi	50.000s	10.017ms	340	350	97.14
V2S	shadow_reg_update_error	aes_shadow_reg_errors	3.000s	117.019us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	3.000s	117.019us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	3.000s	117.019us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	3.000s	117.019us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	4.000s	144.543us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	8.000s	699.704us	5	5	100.00
		aes_tl_intg_err	6.000s	1.793ms	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	6.000s	1.793ms	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	21.000s	1.395ms	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	3.000s	117.019us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	11.000s	483.430us	50	50	100.00
		aes_stress	18.000s	483.632us	50	50	100.00
		aes_alert_reset	21.000s	1.395ms	50	50	100.00
		aes_core_fi	1.250m	10.003ms	68	70	97.14
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	3.000s	117.019us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	4.000s	90.313us	50	50	100.00
		aes_stress	18.000s	483.632us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	18.000s	483.632us	50	50	100.00
		aes_sideload	47.000s	1.533ms	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	4.000s	90.313us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	4.000s	90.313us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	4.000s	90.313us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	4.000s	90.313us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	4.000s	90.313us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	18.000s	483.632us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	18.000s	483.632us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	24.000s	1.646ms	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	24.000s	1.646ms	50	50	100.00
		aes_control_fi	50.000s	10.008ms	270	300	90.00
		aes_cipher_fi	50.000s	10.017ms	340	350	97.14
		aes_ctr_fi	6.000s	545.014us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	24.000s	1.646ms	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	24.000s	1.646ms	50	50	100.00
		aes_control_fi	50.000s	10.008ms	270	300	90.00
		aes_cipher_fi	50.000s	10.017ms	340	350	97.14
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	50.000s	10.017ms	340	350	97.14
V2S	sec_cm_ctr_fsm_sparse	aes_fi	24.000s	1.646ms	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	24.000s	1.646ms	50	50	100.00
		aes_control_fi	50.000s	10.008ms	270	300	90.00
		aes_ctr_fi	6.000s	545.014us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	24.000s	1.646ms	50	50	100.00
		aes_control_fi	50.000s	10.008ms	270	300	90.00
		aes_cipher_fi	50.000s	10.017ms	340	350	97.14
		aes_ctr_fi	6.000s	545.014us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	21.000s	1.395ms	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	24.000s	1.646ms	50	50	100.00
		aes_control_fi	50.000s	10.008ms	270	300	90.00
		aes_cipher_fi	50.000s	10.017ms	340	350	97.14
		aes_ctr_fi	6.000s	545.014us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	24.000s	1.646ms	50	50	100.00
		aes_control_fi	50.000s	10.008ms	270	300	90.00
		aes_cipher_fi	50.000s	10.017ms	340	350	97.14
		aes_ctr_fi	6.000s	545.014us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	24.000s	1.646ms	50	50	100.00
		aes_control_fi	50.000s	10.008ms	270	300	90.00
		aes_ctr_fi	6.000s	545.014us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	24.000s	1.646ms	50	50	100.00
		aes_control_fi	50.000s	10.008ms	270	300	90.00
		aes_cipher_fi	50.000s	10.017ms	340	350	97.14
V2S		TOTAL			943	985	95.74
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	6.683m	38.813ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1550	1602	96.75

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	13	100.00
V2S	11	11	8	72.73
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.32	98.54	96.30	99.42	95.67	97.64	97.78	99.11	96.21

Failure Buckets

Job aes_masked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 23 failures:
- Test aes_control_fi has 21 failures.
  - 17.aes_control_fi.102196564733809467441723202518750926892462263289887216214619052170535657835952
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/17.aes_control_fi/latest/run.log
```
  Job ID: smart:22cf0c8a-d11c-4bc5-8644-97aaeeae7761
```
  - 53.aes_control_fi.37130827444765326070170314288680966635659649396405738089838675743769493362585
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/53.aes_control_fi/latest/run.log
```
  Job ID: smart:fb231167-58db-488b-8b8f-e09ef2edf498
```
  - ... and 19 more failures.
- Test aes_cipher_fi has 2 failures.
  - 229.aes_cipher_fi.52080526202464098917783961938018380970285566991447339712464688520358842323492
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/229.aes_cipher_fi/latest/run.log
```
  Job ID: smart:1c541f0f-33ed-42c9-8f4c-cd814056b8c1
```
  - 247.aes_cipher_fi.110883295160680639630014980650469149892617968558084230209588236510677679373885
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/247.aes_cipher_fi/latest/run.log
```
  Job ID: smart:1ca1ca84-70c7-4b33-a304-6a1f4a69f5a4
```
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 9 failures:
- Test aes_control_fi has 9 failures.
  - 45.aes_control_fi.82190302243275046087827007898736662124610365105791562286567399303630885782364
    Line 325, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/45.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10014095524 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10014095524 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 147.aes_control_fi.112641663865535865644420673940320651016204483718554024421478912396270574676
    Line 313, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/147.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10004991430 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10004991430 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 7 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 8 failures:
- Test aes_cipher_fi has 8 failures.
  - 13.aes_cipher_fi.71877116010613140468147996136303609961562497284993572452947794389160546104238
    Line 319, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/13.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10028890627 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10028890627 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 52.aes_cipher_fi.72606512433583718159456012234154960313389171554445497243690646953200708005132
    Line 323, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/52.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10017472286 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10017472286 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 7 failures:

Test aes_stress_all_with_rand_reset has 7 failures.

0.aes_stress_all_with_rand_reset.108666405728797962783039622330833654766036615636686600209134426662218327394231
Line 1287, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 17931642741 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 17931642741 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.21212293629575010014675265868876802102421999882864666671056155036824893723470
Line 565, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 91680956219 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 91680956219 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 3 failures:

Test aes_stress_all_with_rand_reset has 3 failures.

2.aes_stress_all_with_rand_reset.63727105581871329812881480886337924871453056642869243873139029023427501337885
Line 692, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2862187894 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 2862187894 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.aes_stress_all_with_rand_reset.54412428238261019045092180290073416454348090108292146517138561354321231877425
Line 857, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1352002149 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1352002149 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_core_fi has 2 failures.
  - 53.aes_core_fi.62421876255707381215915217495792159420259010736943943681991793819774592960462
    Line 313, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/53.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10005156999 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10005156999 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 54.aes_core_fi.27430476319268873684331071735703846422606330863384058392640835890870092774513
    Line 315, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/54.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10003306943 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10003306943 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```