AES/MASKED Simulation Results

Friday June 28 2024 23:02:02 UTC

GitHub Revision: `3d5220a43f`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 73442097946972310753089853920865571566707682704390544987111276126114608747389

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	194.419us	1	1	100.00
V1	smoke	aes_smoke	10.000s	221.928us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	58.931us	5	5	100.00
V1	csr_rw	aes_csr_rw	4.000s	82.348us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	9.000s	587.370us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	162.010us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	4.000s	225.756us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	4.000s	82.348us	20	20	100.00
		aes_csr_aliasing	5.000s	162.010us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	10.000s	221.928us	50	50	100.00
		aes_config_error	11.000s	598.211us	50	50	100.00
		aes_stress	30.000s	5.051ms	50	50	100.00
V2	key_length	aes_smoke	10.000s	221.928us	50	50	100.00
		aes_config_error	11.000s	598.211us	50	50	100.00
		aes_stress	30.000s	5.051ms	50	50	100.00
V2	back2back	aes_stress	30.000s	5.051ms	50	50	100.00
		aes_b2b	38.000s	1.722ms	50	50	100.00
V2	backpressure	aes_stress	30.000s	5.051ms	50	50	100.00
V2	multi_message	aes_smoke	10.000s	221.928us	50	50	100.00
		aes_config_error	11.000s	598.211us	50	50	100.00
		aes_stress	30.000s	5.051ms	50	50	100.00
		aes_alert_reset	17.000s	640.950us	50	50	100.00
V2	failure_test	aes_man_cfg_err	6.000s	149.156us	50	50	100.00
		aes_config_error	11.000s	598.211us	50	50	100.00
		aes_alert_reset	17.000s	640.950us	50	50	100.00
V2	trigger_clear_test	aes_clear	15.000s	318.529us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	13.000s	383.610us	1	1	100.00
V2	reset_recovery	aes_alert_reset	17.000s	640.950us	50	50	100.00
V2	stress	aes_stress	30.000s	5.051ms	50	50	100.00
V2	sideload	aes_stress	30.000s	5.051ms	50	50	100.00
		aes_sideload	18.000s	468.991us	50	50	100.00
V2	deinitialization	aes_deinit	8.000s	600.852us	50	50	100.00
V2	stress_all	aes_stress_all	1.467m	4.969ms	10	10	100.00
V2	alert_test	aes_alert_test	8.000s	60.231us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	6.000s	90.955us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	6.000s	90.955us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	58.931us	5	5	100.00
		aes_csr_rw	4.000s	82.348us	20	20	100.00
		aes_csr_aliasing	5.000s	162.010us	5	5	100.00
		aes_same_csr_outstanding	5.000s	56.302us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	58.931us	5	5	100.00
		aes_csr_rw	4.000s	82.348us	20	20	100.00
		aes_csr_aliasing	5.000s	162.010us	5	5	100.00
		aes_same_csr_outstanding	5.000s	56.302us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	19.000s	634.638us	50	50	100.00
V2S	fault_inject	aes_fi	14.000s	446.803us	50	50	100.00
		aes_control_fi	43.000s	10.043ms	283	300	94.33
		aes_cipher_fi	48.000s	10.006ms	336	350	96.00
V2S	shadow_reg_update_error	aes_shadow_reg_errors	4.000s	291.747us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	4.000s	291.747us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	4.000s	291.747us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	4.000s	291.747us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	5.000s	501.462us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	8.000s	2.127ms	5	5	100.00
		aes_tl_intg_err	7.000s	1.019ms	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	7.000s	1.019ms	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	17.000s	640.950us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	4.000s	291.747us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	10.000s	221.928us	50	50	100.00
		aes_stress	30.000s	5.051ms	50	50	100.00
		aes_alert_reset	17.000s	640.950us	50	50	100.00
		aes_core_fi	1.517m	10.069ms	66	70	94.29
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	4.000s	291.747us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	6.000s	86.705us	50	50	100.00
		aes_stress	30.000s	5.051ms	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	30.000s	5.051ms	50	50	100.00
		aes_sideload	18.000s	468.991us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	6.000s	86.705us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	6.000s	86.705us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	6.000s	86.705us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	6.000s	86.705us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	6.000s	86.705us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	30.000s	5.051ms	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	30.000s	5.051ms	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	14.000s	446.803us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	14.000s	446.803us	50	50	100.00
		aes_control_fi	43.000s	10.043ms	283	300	94.33
		aes_cipher_fi	48.000s	10.006ms	336	350	96.00
		aes_ctr_fi	5.000s	224.928us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	14.000s	446.803us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	14.000s	446.803us	50	50	100.00
		aes_control_fi	43.000s	10.043ms	283	300	94.33
		aes_cipher_fi	48.000s	10.006ms	336	350	96.00
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	48.000s	10.006ms	336	350	96.00
V2S	sec_cm_ctr_fsm_sparse	aes_fi	14.000s	446.803us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	14.000s	446.803us	50	50	100.00
		aes_control_fi	43.000s	10.043ms	283	300	94.33
		aes_ctr_fi	5.000s	224.928us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	14.000s	446.803us	50	50	100.00
		aes_control_fi	43.000s	10.043ms	283	300	94.33
		aes_cipher_fi	48.000s	10.006ms	336	350	96.00
		aes_ctr_fi	5.000s	224.928us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	17.000s	640.950us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	14.000s	446.803us	50	50	100.00
		aes_control_fi	43.000s	10.043ms	283	300	94.33
		aes_cipher_fi	48.000s	10.006ms	336	350	96.00
		aes_ctr_fi	5.000s	224.928us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	14.000s	446.803us	50	50	100.00
		aes_control_fi	43.000s	10.043ms	283	300	94.33
		aes_cipher_fi	48.000s	10.006ms	336	350	96.00
		aes_ctr_fi	5.000s	224.928us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	14.000s	446.803us	50	50	100.00
		aes_control_fi	43.000s	10.043ms	283	300	94.33
		aes_ctr_fi	5.000s	224.928us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	14.000s	446.803us	50	50	100.00
		aes_control_fi	43.000s	10.043ms	283	300	94.33
		aes_cipher_fi	48.000s	10.006ms	336	350	96.00
V2S		TOTAL			950	985	96.45
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	10.267m	18.263ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1557	1602	97.19

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	13	100.00
V2S	11	11	8	72.73
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.38	98.56	96.34	99.45	95.80	97.72	100.00	99.11	97.21

Failure Buckets

Job aes_masked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 20 failures:
- Test aes_cipher_fi has 6 failures.
  - 37.aes_cipher_fi.66185235730466277655514752329907305979673056981318755205517526330571542737824
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/37.aes_cipher_fi/latest/run.log
```
  Job ID: smart:20f7e2f8-6c6a-42b5-854d-28c40b8f408e
```
  - 100.aes_cipher_fi.4677879229271742992108276660725648588427691070151000493028874102814291203306
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/100.aes_cipher_fi/latest/run.log
```
  Job ID: smart:51ea49f4-a8f9-46d2-a96a-e746324e5566
```
  - ... and 4 more failures.
- Test aes_control_fi has 14 failures.
  - 40.aes_control_fi.58656772288248977962121935459193069838522061776693952907122217526358717595974
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/40.aes_control_fi/latest/run.log
```
  Job ID: smart:be8321cc-8122-4917-98cf-07cbbc690f9e
```
  - 68.aes_control_fi.74991798366829574008795906464278427840290808104999811846062571654080750849804
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/68.aes_control_fi/latest/run.log
```
  Job ID: smart:b2e0cde6-92b3-4ec9-b28e-41cb004b25ad
```
  - ... and 12 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 8 failures:
- Test aes_cipher_fi has 8 failures.
  - 10.aes_cipher_fi.96150556071557787600135071993547381999466856958667040751238667175439260435784
    Line 316, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/10.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10006282630 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006282630 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 117.aes_cipher_fi.69989818689148414010042972514519591454909332090214026528291916741712446335271
    Line 328, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/117.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10006469942 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006469942 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues

has 7 failures:

Test aes_stress_all_with_rand_reset has 7 failures.

0.aes_stress_all_with_rand_reset.48650469862520721799036082531748244738923021243465013120974189285129887481966
Line 991, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 6012660318 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 6012660318 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.81435533679364449568430503775598078863439603924757584560806286778205377726172
Line 524, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 595981783 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 595981783 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues

has 3 failures:

Test aes_stress_all_with_rand_reset has 3 failures.

3.aes_stress_all_with_rand_reset.18972226971684802766451157094762479057150032417905341770309127855641109976274
Line 1497, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1443118733 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1443118733 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.aes_stress_all_with_rand_reset.6703248323281781917798399602237875566008228956389578463415726877350662087597
Line 1419, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/4.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 709006867 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 709006867 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 3 failures:
- Test aes_core_fi has 3 failures.
  - 18.aes_core_fi.52721138693258905002923116940748577173810828082492997840949806013638487386870
    Line 324, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/18.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10003514346 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10003514346 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 36.aes_core_fi.9192313476976553624193457430168457999433140311442401501809544187280628276240
    Line 323, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/36.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10016239478 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10016239478 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 3 failures:
- Test aes_control_fi has 3 failures.
  - 194.aes_control_fi.86029689429534652630704075365811174025811866184851572649031988035288006978660
    Line 323, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/194.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10043156521 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10043156521 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 239.aes_control_fi.111990824031326599212442965345594124064523605444056171908293209255408874827543
    Line 310, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/239.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10017364362 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10017364362 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=*) == * has 1 failures:
- Test aes_core_fi has 1 failures.
  - 56.aes_core_fi.25131460912740712944353651633000538827219531739216830520071091524607919474615
    Line 312, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/56.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10068504322 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0x14631284) == 0x0
  UVM_INFO @ 10068504322 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```