AES/MASKED Simulation Results

Thursday June 27 2024 23:02:31 UTC

GitHub Revision: `8db2a18db1`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 100513533386727882033709335126269317053614297947080434367729937568368619502352

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	91.876us	1	1	100.00
V1	smoke	aes_smoke	26.000s	728.937us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	114.998us	5	5	100.00
V1	csr_rw	aes_csr_rw	4.000s	77.123us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	11.000s	1.152ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	310.818us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	3.000s	133.766us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	4.000s	77.123us	20	20	100.00
		aes_csr_aliasing	5.000s	310.818us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	26.000s	728.937us	50	50	100.00
		aes_config_error	12.000s	176.045us	50	50	100.00
		aes_stress	37.000s	3.471ms	50	50	100.00
V2	key_length	aes_smoke	26.000s	728.937us	50	50	100.00
		aes_config_error	12.000s	176.045us	50	50	100.00
		aes_stress	37.000s	3.471ms	50	50	100.00
V2	back2back	aes_stress	37.000s	3.471ms	50	50	100.00
		aes_b2b	1.000m	947.939us	50	50	100.00
V2	backpressure	aes_stress	37.000s	3.471ms	50	50	100.00
V2	multi_message	aes_smoke	26.000s	728.937us	50	50	100.00
		aes_config_error	12.000s	176.045us	50	50	100.00
		aes_stress	37.000s	3.471ms	50	50	100.00
		aes_alert_reset	20.000s	925.719us	50	50	100.00
V2	failure_test	aes_man_cfg_err	6.000s	295.379us	50	50	100.00
		aes_config_error	12.000s	176.045us	50	50	100.00
		aes_alert_reset	20.000s	925.719us	50	50	100.00
V2	trigger_clear_test	aes_clear	29.000s	3.217ms	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	13.000s	335.380us	1	1	100.00
V2	reset_recovery	aes_alert_reset	20.000s	925.719us	50	50	100.00
V2	stress	aes_stress	37.000s	3.471ms	50	50	100.00
V2	sideload	aes_stress	37.000s	3.471ms	50	50	100.00
		aes_sideload	36.000s	4.152ms	50	50	100.00
V2	deinitialization	aes_deinit	25.000s	1.251ms	50	50	100.00
V2	stress_all	aes_stress_all	1.333m	3.534ms	10	10	100.00
V2	alert_test	aes_alert_test	5.000s	127.959us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	6.000s	196.975us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	6.000s	196.975us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	114.998us	5	5	100.00
		aes_csr_rw	4.000s	77.123us	20	20	100.00
		aes_csr_aliasing	5.000s	310.818us	5	5	100.00
		aes_same_csr_outstanding	4.000s	126.505us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	114.998us	5	5	100.00
		aes_csr_rw	4.000s	77.123us	20	20	100.00
		aes_csr_aliasing	5.000s	310.818us	5	5	100.00
		aes_same_csr_outstanding	4.000s	126.505us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	34.000s	1.214ms	50	50	100.00
V2S	fault_inject	aes_fi	15.000s	821.603us	50	50	100.00
		aes_control_fi	44.000s	10.007ms	280	300	93.33
		aes_cipher_fi	47.000s	10.010ms	335	350	95.71
V2S	shadow_reg_update_error	aes_shadow_reg_errors	4.000s	75.247us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	4.000s	75.247us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	4.000s	75.247us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	4.000s	75.247us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	4.000s	97.619us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	9.000s	528.623us	5	5	100.00
		aes_tl_intg_err	6.000s	445.694us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	6.000s	445.694us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	20.000s	925.719us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	4.000s	75.247us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	26.000s	728.937us	50	50	100.00
		aes_stress	37.000s	3.471ms	50	50	100.00
		aes_alert_reset	20.000s	925.719us	50	50	100.00
		aes_core_fi	1.333m	10.013ms	65	70	92.86
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	4.000s	75.247us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	9.000s	324.334us	50	50	100.00
		aes_stress	37.000s	3.471ms	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	37.000s	3.471ms	50	50	100.00
		aes_sideload	36.000s	4.152ms	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	9.000s	324.334us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	9.000s	324.334us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	9.000s	324.334us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	9.000s	324.334us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	9.000s	324.334us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	37.000s	3.471ms	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	37.000s	3.471ms	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	15.000s	821.603us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	15.000s	821.603us	50	50	100.00
		aes_control_fi	44.000s	10.007ms	280	300	93.33
		aes_cipher_fi	47.000s	10.010ms	335	350	95.71
		aes_ctr_fi	5.000s	163.102us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	15.000s	821.603us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	15.000s	821.603us	50	50	100.00
		aes_control_fi	44.000s	10.007ms	280	300	93.33
		aes_cipher_fi	47.000s	10.010ms	335	350	95.71
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	47.000s	10.010ms	335	350	95.71
V2S	sec_cm_ctr_fsm_sparse	aes_fi	15.000s	821.603us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	15.000s	821.603us	50	50	100.00
		aes_control_fi	44.000s	10.007ms	280	300	93.33
		aes_ctr_fi	5.000s	163.102us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	15.000s	821.603us	50	50	100.00
		aes_control_fi	44.000s	10.007ms	280	300	93.33
		aes_cipher_fi	47.000s	10.010ms	335	350	95.71
		aes_ctr_fi	5.000s	163.102us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	20.000s	925.719us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	15.000s	821.603us	50	50	100.00
		aes_control_fi	44.000s	10.007ms	280	300	93.33
		aes_cipher_fi	47.000s	10.010ms	335	350	95.71
		aes_ctr_fi	5.000s	163.102us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	15.000s	821.603us	50	50	100.00
		aes_control_fi	44.000s	10.007ms	280	300	93.33
		aes_cipher_fi	47.000s	10.010ms	335	350	95.71
		aes_ctr_fi	5.000s	163.102us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	15.000s	821.603us	50	50	100.00
		aes_control_fi	44.000s	10.007ms	280	300	93.33
		aes_ctr_fi	5.000s	163.102us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	15.000s	821.603us	50	50	100.00
		aes_control_fi	44.000s	10.007ms	280	300	93.33
		aes_cipher_fi	47.000s	10.010ms	335	350	95.71
V2S		TOTAL			945	985	95.94
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	1.017m	697.403us	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1552	1602	96.88

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	13	100.00
V2S	11	11	8	72.73
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.30	98.48	96.14	99.38	95.78	97.72	97.78	98.96	97.41

Failure Buckets

Job aes_masked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 17 failures:
- Test aes_cipher_fi has 6 failures.
  - 2.aes_cipher_fi.44629717019204776100802262378794340618122458882339176185656157134090477515426
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/2.aes_cipher_fi/latest/run.log
```
  Job ID: smart:c51455ad-bba7-4e9e-ad79-ea661b8ca175
```
  - 28.aes_cipher_fi.10766104049878284821934888846555895226309593575445554842073463270778413949534
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/28.aes_cipher_fi/latest/run.log
```
  Job ID: smart:255d839e-3e36-4d02-94f8-cbb0369e354f
```
  - ... and 4 more failures.
- Test aes_control_fi has 11 failures.
  - 5.aes_control_fi.101295848572407432376181267764080654853154750962829033290427990376590811342917
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/5.aes_control_fi/latest/run.log
```
  Job ID: smart:a105093e-8e58-48c3-a78d-88d81cf80819
```
  - 13.aes_control_fi.32266269090210357022209011969691449199490984579715919042895258869969389463765
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/13.aes_control_fi/latest/run.log
```
  Job ID: smart:8205555a-bc7d-4814-9321-f768dc50b857
```
  - ... and 9 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 9 failures:
- Test aes_control_fi has 9 failures.
  - 16.aes_control_fi.5471454446882323903544987561086116064447211270145314168180070723473722731159
    Line 322, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/16.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10043603024 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10043603024 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 107.aes_control_fi.74300804287936167322056950772397878249221947043955060307200884198111056522957
    Line 323, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/107.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10022073459 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10022073459 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 7 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 9 failures:
- Test aes_cipher_fi has 9 failures.
  - 74.aes_cipher_fi.23871528206861693150261677505811285830676202611781124039834113430903829736965
    Line 325, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/74.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10010816659 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10010816659 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 127.aes_cipher_fi.16219286679788525570039235560959180569274622789151518048047498423157171184116
    Line 311, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/127.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10012792007 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10012792007 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 7 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 6 failures:

Test aes_stress_all_with_rand_reset has 6 failures.

0.aes_stress_all_with_rand_reset.10568074208600271862838818568430239081717768216542594807511526142547976315264
Line 1283, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1585022105 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1585022105 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.aes_stress_all_with_rand_reset.49388425733792000907490957389171402075091635171188716912523003675538889943716
Line 1439, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1967174103 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1967174103 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 4 failures:
- Test aes_core_fi has 4 failures.
  - 13.aes_core_fi.65277474552323899942618299372411839762359684033557523387544193566201062361751
    Line 321, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/13.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10058357192 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10058357192 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 21.aes_core_fi.36491714462086054412093396305496001650854098880397225446029938731881705777713
    Line 317, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/21.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10013898473 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10013898473 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 2 failures:

Test aes_stress_all_with_rand_reset has 2 failures.

4.aes_stress_all_with_rand_reset.95593496502878324750554693259438465419682360562067088513415153741193537990260
Line 1490, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/4.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 794311749 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 794311749 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

7.aes_stress_all_with_rand_reset.113994547414915495312506399361460311387500422595833172735168309171954085724506
Line 573, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/7.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 203968856 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 203968856 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:829) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 1.aes_stress_all_with_rand_reset.2011539852015625170598115508261607968689943140047998225023664907954898816825
    Line 701, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 665403343 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 665403343 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_reseed_vseq.sv:40) [aes_reseed_vseq] Check failed request_seen | finished_all_msgs == *'b* (* [*] vs * [*]) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 8.aes_stress_all_with_rand_reset.60682186828618118299430807588322928181602973172787662390279621843255405073699
    Line 487, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/8.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 364850396 ps: (aes_reseed_vseq.sv:40) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed request_seen | finished_all_msgs == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 364850396 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_*/rtl/aes_cipher_core.sv,858): Assertion AesSecCmKeyMaskingInitialPrngUpdateSubBytes has failed (* cycles, starting * PS) has 1 failures:

Test aes_core_fi has 1 failures.

34.aes_core_fi.33194871350816762041711429992502419231899739643066695027667903810903866244449
Line 314, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/34.aes_core_fi/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_cipher_core.sv,858): (time 8978142 PS) Assertion tb.dut.u_aes_core.u_aes_cipher_core.gen_sec_cm_key_masking_svas.AesSecCmKeyMaskingInitialPrngUpdateSubBytes has failed (2 cycles, starting 8966514 PS)
            (SecAllowForcingMasks && force_masks_i) || dec_key_gen_o == SP2V_HIGH)
                                                                                 |
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_cipher_core.sv,865): (time 8978142 PS) Assertion tb.dut.u_aes_core.u_aes_cipher_core.gen_sec_cm_key_masking_svas.AesSecCmKeyMaskingInitialPrngUpdateKeyExpand has failed (2 cycles, starting 8966514 PS)
  UVM_ERROR @   8978142 ps: (aes_cipher_core.sv:858) [ASSERT FAILED] AesSecCmKeyMaskingInitialPrngUpdateSubBytes