AES/MASKED Simulation Results

Tuesday July 09 2024 23:02:48 UTC

GitHub Revision: `6a84251492`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 61727890964832844865465694323650730626175387240181955975848876152363892893427

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	4.000s	129.177us	1	1	100.00
V1	smoke	aes_smoke	15.000s	476.281us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	8.000s	87.709us	5	5	100.00
V1	csr_rw	aes_csr_rw	5.400m	10.004ms	19	20	95.00
V1	csr_bit_bash	aes_csr_bit_bash	13.000s	4.922ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	4.000s	124.206us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	5.000s	482.548us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	5.400m	10.004ms	19	20	95.00
		aes_csr_aliasing	4.000s	124.206us	5	5	100.00
V1		TOTAL			105	106	99.06
V2	algorithm	aes_smoke	15.000s	476.281us	50	50	100.00
		aes_config_error	54.000s	1.924ms	50	50	100.00
		aes_stress	1.750m	6.919ms	50	50	100.00
V2	key_length	aes_smoke	15.000s	476.281us	50	50	100.00
		aes_config_error	54.000s	1.924ms	50	50	100.00
		aes_stress	1.750m	6.919ms	50	50	100.00
V2	back2back	aes_stress	1.750m	6.919ms	50	50	100.00
		aes_b2b	33.000s	415.176us	50	50	100.00
V2	backpressure	aes_stress	1.750m	6.919ms	50	50	100.00
V2	multi_message	aes_smoke	15.000s	476.281us	50	50	100.00
		aes_config_error	54.000s	1.924ms	50	50	100.00
		aes_stress	1.750m	6.919ms	50	50	100.00
		aes_alert_reset	13.000s	390.366us	50	50	100.00
V2	failure_test	aes_man_cfg_err	6.000s	151.468us	50	50	100.00
		aes_config_error	54.000s	1.924ms	50	50	100.00
		aes_alert_reset	13.000s	390.366us	50	50	100.00
V2	trigger_clear_test	aes_clear	1.000m	8.199ms	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	14.000s	1.019ms	1	1	100.00
V2	reset_recovery	aes_alert_reset	13.000s	390.366us	50	50	100.00
V2	stress	aes_stress	1.750m	6.919ms	50	50	100.00
V2	sideload	aes_stress	1.750m	6.919ms	50	50	100.00
		aes_sideload	15.000s	1.494ms	50	50	100.00
V2	deinitialization	aes_deinit	1.083m	2.486ms	50	50	100.00
V2	stress_all	aes_stress_all	1.233m	12.123ms	9	10	90.00
V2	alert_test	aes_alert_test	4.000s	150.795us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	5.000s	98.229us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	5.000s	98.229us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	8.000s	87.709us	5	5	100.00
		aes_csr_rw	5.400m	10.004ms	19	20	95.00
		aes_csr_aliasing	4.000s	124.206us	5	5	100.00
		aes_same_csr_outstanding	4.000s	129.230us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	8.000s	87.709us	5	5	100.00
		aes_csr_rw	5.400m	10.004ms	19	20	95.00
		aes_csr_aliasing	4.000s	124.206us	5	5	100.00
		aes_same_csr_outstanding	4.000s	129.230us	20	20	100.00
V2		TOTAL			500	501	99.80
V2S	reseeding	aes_reseed	22.000s	782.120us	48	50	96.00
V2S	fault_inject	aes_fi	14.000s	465.160us	49	50	98.00
		aes_control_fi	51.000s	10.006ms	282	300	94.00
		aes_cipher_fi	35.000s	10.009ms	338	350	96.57
V2S	shadow_reg_update_error	aes_shadow_reg_errors	3.000s	97.255us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	3.000s	97.255us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	3.000s	97.255us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	3.000s	97.255us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	4.000s	80.085us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	9.000s	536.910us	5	5	100.00
		aes_tl_intg_err	5.000s	512.888us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	5.000s	512.888us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	13.000s	390.366us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	3.000s	97.255us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	15.000s	476.281us	50	50	100.00
		aes_stress	1.750m	6.919ms	50	50	100.00
		aes_alert_reset	13.000s	390.366us	50	50	100.00
		aes_core_fi	1.367m	10.006ms	68	70	97.14
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	3.000s	97.255us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	5.000s	142.650us	50	50	100.00
		aes_stress	1.750m	6.919ms	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	1.750m	6.919ms	50	50	100.00
		aes_sideload	15.000s	1.494ms	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	5.000s	142.650us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	5.000s	142.650us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	5.000s	142.650us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	5.000s	142.650us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	5.000s	142.650us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	1.750m	6.919ms	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	1.750m	6.919ms	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	14.000s	465.160us	49	50	98.00
V2S	sec_cm_main_fsm_redun	aes_fi	14.000s	465.160us	49	50	98.00
		aes_control_fi	51.000s	10.006ms	282	300	94.00
		aes_cipher_fi	35.000s	10.009ms	338	350	96.57
		aes_ctr_fi	5.000s	244.189us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	14.000s	465.160us	49	50	98.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	14.000s	465.160us	49	50	98.00
		aes_control_fi	51.000s	10.006ms	282	300	94.00
		aes_cipher_fi	35.000s	10.009ms	338	350	96.57
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	35.000s	10.009ms	338	350	96.57
V2S	sec_cm_ctr_fsm_sparse	aes_fi	14.000s	465.160us	49	50	98.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	14.000s	465.160us	49	50	98.00
		aes_control_fi	51.000s	10.006ms	282	300	94.00
		aes_ctr_fi	5.000s	244.189us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	14.000s	465.160us	49	50	98.00
		aes_control_fi	51.000s	10.006ms	282	300	94.00
		aes_cipher_fi	35.000s	10.009ms	338	350	96.57
		aes_ctr_fi	5.000s	244.189us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	13.000s	390.366us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	14.000s	465.160us	49	50	98.00
		aes_control_fi	51.000s	10.006ms	282	300	94.00
		aes_cipher_fi	35.000s	10.009ms	338	350	96.57
		aes_ctr_fi	5.000s	244.189us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	14.000s	465.160us	49	50	98.00
		aes_control_fi	51.000s	10.006ms	282	300	94.00
		aes_cipher_fi	35.000s	10.009ms	338	350	96.57
		aes_ctr_fi	5.000s	244.189us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	14.000s	465.160us	49	50	98.00
		aes_control_fi	51.000s	10.006ms	282	300	94.00
		aes_ctr_fi	5.000s	244.189us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	14.000s	465.160us	49	50	98.00
		aes_control_fi	51.000s	10.006ms	282	300	94.00
		aes_cipher_fi	35.000s	10.009ms	338	350	96.57
V2S		TOTAL			950	985	96.45
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	2.450m	10.226ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1555	1602	97.07

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	6	85.71
V2	13	13	12	92.31
V2S	11	11	6	54.55
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.34	98.53	96.25	99.45	95.67	97.72	100.00	99.11	96.81

Failure Buckets

Job aes_masked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 15 failures:
- Test aes_control_fi has 10 failures.
  - 9.aes_control_fi.29187865336966418277827074672848833887917866622655590383044561778465309139781
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/9.aes_control_fi/latest/run.log
```
  Job ID: smart:e650b624-2433-41dd-97d9-b346e8f5fbd6
```
  - 57.aes_control_fi.46517634938634472376846325015667624742996183748597354109524487922168101422616
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/57.aes_control_fi/latest/run.log
```
  Job ID: smart:0d5ee73e-e45e-4b15-846f-bb2cdeeb3e7f
```
  - ... and 8 more failures.
- Test aes_cipher_fi has 5 failures.
  - 9.aes_cipher_fi.73682801588301365289632666055862459411388226157226490117451740207394068118160
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/9.aes_cipher_fi/latest/run.log
```
  Job ID: smart:4ecd3366-dc32-459b-981f-15be714538bd
```
  - 37.aes_cipher_fi.69212440841857318776920642926801765072464423720302467809301730765507141492424
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/37.aes_cipher_fi/latest/run.log
```
  Job ID: smart:d8291979-e410-4424-b398-32883bf26c2c
```
  - ... and 3 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 8 failures:

Test aes_stress_all_with_rand_reset has 8 failures.

0.aes_stress_all_with_rand_reset.108361407462375155510780183446708137359788392883921277370631904042683974260833
Line 937, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 411094341 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 411094341 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.100108536214685055955738781307812019835192512005684141299305655962315626171345
Line 1219, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 10225961070 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 10225961070 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 8 failures:
- Test aes_control_fi has 8 failures.
  - 27.aes_control_fi.38814701686015267443987092144952212124691415098199249347753095798952437388462
    Line 317, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/27.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10023118958 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10023118958 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 48.aes_control_fi.37000149747414049735536832825266690724113410043553859469043372275487795589746
    Line 317, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/48.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10090895377 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10090895377 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 7 failures:
- Test aes_cipher_fi has 7 failures.
  - 46.aes_cipher_fi.103597080296661585551350759633709859510721416102891488330553132115547199562916
    Line 322, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/46.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10039711304 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10039711304 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 54.aes_cipher_fi.50523821106806647241982187053694271829926396912157613240808912550994495314522
    Line 319, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/54.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10019488690 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10019488690 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,987): Assertion AesSecCmDataRegLocalEscDataOut has failed (* cycles, starting * PS) has 2 failures:

Test aes_stress_all has 1 failures.

3.aes_stress_all.81592507000308255304212602948015340768227104119711150042908722416099448255869
Line 67488, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/3.aes_stress_all/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,987): (time 2128359946 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 2128339538 PS)
  UVM_ERROR @ 2128359946 ps: (aes_core.sv:987) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut
  UVM_INFO @ 2128359946 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test aes_fi has 1 failures.

36.aes_fi.110739501457980849774704586690615865264050509738565078274356951230060961013768
Line 2878, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/36.aes_fi/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,987): (time 7369029 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 7358825 PS)
  UVM_ERROR @   7369029 ps: (aes_core.sv:987) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut
  UVM_INFO @   7369029 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_core_fi has 2 failures.
  - 8.aes_core_fi.85991150904149189836492159997633632586536411569564659916119981640886884802354
    Line 322, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/8.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10006319238 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006319238 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 18.aes_core_fi.90017013578412824322740161859897199320137172499489490486911979366345054463547
    Line 313, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/18.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10008343282 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10008343282 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.output_valid (addr=*) == * has 1 failures:
- Test aes_csr_rw has 1 failures.
  - 2.aes_csr_rw.50205632321499468475781231891572086674481291303217123433390145847982912745196
    Line 284, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/2.aes_csr_rw/latest/run.log
```
  UVM_FATAL @ 10004020380 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.output_valid (addr=0x8d02f884) == 0x0
  UVM_INFO @ 10004020380 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:826) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 5.aes_stress_all_with_rand_reset.7677654138507024193257340050961077479889811655196957493526501201394830354953
    Line 560, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/5.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 669240786 ps: (cip_base_vseq.sv:826) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 669240786 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 8.aes_stress_all_with_rand_reset.24552608321762576987381998249129439050822181250323953327476438916229477240323
    Line 1839, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/8.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1894936108 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1894936108 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_reseed_vseq.sv:28) [aes_reseed_vseq] Check failed request_seen == *'b* (* [*] vs * [*]) has 1 failures:
- Test aes_reseed has 1 failures.
  - 10.aes_reseed.74983539306530092177692260061348160470009378264924626892192451404741098617355
    Line 389, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/10.aes_reseed/latest/run.log
```
  UVM_FATAL @  64741930 ps: (aes_reseed_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed request_seen == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @  64741930 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_reseed_vseq.sv:40) [aes_reseed_vseq] Check failed request_seen | finished_all_msgs == *'b* (* [*] vs * [*]) has 1 failures:
- Test aes_reseed has 1 failures.
  - 12.aes_reseed.11539987207637666689061530048543546098025744955903411453772380393181887899245
    Line 6152, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/12.aes_reseed/latest/run.log
```
  UVM_FATAL @ 362486914 ps: (aes_reseed_vseq.sv:40) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed request_seen | finished_all_msgs == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 362486914 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```