AES/MASKED Simulation Results

Friday July 26 2024 23:02:17 UTC

GitHub Revision: `4877b481e8`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 32772136499307530671572864311472020383177374948143841887013058662761887638244

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	14.000s	53.746us	1	1	100.00
V1	smoke	aes_smoke	10.000s	169.418us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	90.128us	5	5	100.00
V1	csr_rw	aes_csr_rw	8.000s	129.658us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	9.000s	328.197us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	213.951us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	4.000s	59.809us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	8.000s	129.658us	20	20	100.00
		aes_csr_aliasing	5.000s	213.951us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	10.000s	169.418us	50	50	100.00
		aes_config_error	50.000s	2.086ms	50	50	100.00
		aes_stress	19.000s	66.941us	50	50	100.00
V2	key_length	aes_smoke	10.000s	169.418us	50	50	100.00
		aes_config_error	50.000s	2.086ms	50	50	100.00
		aes_stress	19.000s	66.941us	50	50	100.00
V2	back2back	aes_stress	19.000s	66.941us	50	50	100.00
		aes_b2b	1.233m	936.599us	50	50	100.00
V2	backpressure	aes_stress	19.000s	66.941us	50	50	100.00
V2	multi_message	aes_smoke	10.000s	169.418us	50	50	100.00
		aes_config_error	50.000s	2.086ms	50	50	100.00
		aes_stress	19.000s	66.941us	50	50	100.00
		aes_alert_reset	41.000s	1.588ms	50	50	100.00
V2	failure_test	aes_man_cfg_err	10.000s	188.644us	50	50	100.00
		aes_config_error	50.000s	2.086ms	50	50	100.00
		aes_alert_reset	41.000s	1.588ms	50	50	100.00
V2	trigger_clear_test	aes_clear	30.000s	1.625ms	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	32.000s	2.607ms	1	1	100.00
V2	reset_recovery	aes_alert_reset	41.000s	1.588ms	50	50	100.00
V2	stress	aes_stress	19.000s	66.941us	50	50	100.00
V2	sideload	aes_stress	19.000s	66.941us	50	50	100.00
		aes_sideload	43.000s	2.553ms	50	50	100.00
V2	deinitialization	aes_deinit	42.000s	2.240ms	50	50	100.00
V2	stress_all	aes_stress_all	1.633m	2.884ms	10	10	100.00
V2	alert_test	aes_alert_test	9.000s	57.295us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	14.000s	84.410us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	14.000s	84.410us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	90.128us	5	5	100.00
		aes_csr_rw	8.000s	129.658us	20	20	100.00
		aes_csr_aliasing	5.000s	213.951us	5	5	100.00
		aes_same_csr_outstanding	14.000s	1.017ms	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	90.128us	5	5	100.00
		aes_csr_rw	8.000s	129.658us	20	20	100.00
		aes_csr_aliasing	5.000s	213.951us	5	5	100.00
		aes_same_csr_outstanding	14.000s	1.017ms	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	1.217m	2.261ms	50	50	100.00
V2S	fault_inject	aes_fi	11.000s	314.604us	50	50	100.00
		aes_control_fi	46.000s	10.007ms	288	300	96.00
		aes_cipher_fi	48.000s	10.007ms	341	350	97.43
V2S	shadow_reg_update_error	aes_shadow_reg_errors	7.000s	120.180us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	7.000s	120.180us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	7.000s	120.180us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	7.000s	120.180us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	4.000s	156.313us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	10.000s	5.618ms	5	5	100.00
		aes_tl_intg_err	9.000s	157.427us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	9.000s	157.427us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	41.000s	1.588ms	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	7.000s	120.180us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	10.000s	169.418us	50	50	100.00
		aes_stress	19.000s	66.941us	50	50	100.00
		aes_alert_reset	41.000s	1.588ms	50	50	100.00
		aes_core_fi	1.567m	10.088ms	67	70	95.71
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	7.000s	120.180us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	10.000s	367.976us	50	50	100.00
		aes_stress	19.000s	66.941us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	19.000s	66.941us	50	50	100.00
		aes_sideload	43.000s	2.553ms	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	10.000s	367.976us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	10.000s	367.976us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	10.000s	367.976us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	10.000s	367.976us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	10.000s	367.976us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	19.000s	66.941us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	19.000s	66.941us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	11.000s	314.604us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	11.000s	314.604us	50	50	100.00
		aes_control_fi	46.000s	10.007ms	288	300	96.00
		aes_cipher_fi	48.000s	10.007ms	341	350	97.43
		aes_ctr_fi	9.000s	59.554us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	11.000s	314.604us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	11.000s	314.604us	50	50	100.00
		aes_control_fi	46.000s	10.007ms	288	300	96.00
		aes_cipher_fi	48.000s	10.007ms	341	350	97.43
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	48.000s	10.007ms	341	350	97.43
V2S	sec_cm_ctr_fsm_sparse	aes_fi	11.000s	314.604us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	11.000s	314.604us	50	50	100.00
		aes_control_fi	46.000s	10.007ms	288	300	96.00
		aes_ctr_fi	9.000s	59.554us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	11.000s	314.604us	50	50	100.00
		aes_control_fi	46.000s	10.007ms	288	300	96.00
		aes_cipher_fi	48.000s	10.007ms	341	350	97.43
		aes_ctr_fi	9.000s	59.554us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	41.000s	1.588ms	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	11.000s	314.604us	50	50	100.00
		aes_control_fi	46.000s	10.007ms	288	300	96.00
		aes_cipher_fi	48.000s	10.007ms	341	350	97.43
		aes_ctr_fi	9.000s	59.554us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	11.000s	314.604us	50	50	100.00
		aes_control_fi	46.000s	10.007ms	288	300	96.00
		aes_cipher_fi	48.000s	10.007ms	341	350	97.43
		aes_ctr_fi	9.000s	59.554us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	11.000s	314.604us	50	50	100.00
		aes_control_fi	46.000s	10.007ms	288	300	96.00
		aes_ctr_fi	9.000s	59.554us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	11.000s	314.604us	50	50	100.00
		aes_control_fi	46.000s	10.007ms	288	300	96.00
		aes_cipher_fi	48.000s	10.007ms	341	350	97.43
V2S		TOTAL			961	985	97.56
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	2.700m	5.801ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1568	1602	97.88

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	13	100.00
V2S	11	11	8	72.73
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.33	98.53	96.25	99.42	95.83	97.64	97.78	98.96	96.41

Failure Buckets

Job aes_masked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 15 failures:
- Test aes_control_fi has 11 failures.
  - 27.aes_control_fi.43614391881843559504203540357265802354443491238644586591507785717285166497231
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/27.aes_control_fi/latest/run.log
```
  Job ID: smart:4913df74-9477-42a1-b4ba-a0c0c1a6a63f
```
  - 36.aes_control_fi.17619308468267554176389273463918613734272666036319189612382504635906353165213
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/36.aes_control_fi/latest/run.log
```
  Job ID: smart:439b2e4a-2046-4feb-9a9d-6223d6706c79
```
  - ... and 9 more failures.
- Test aes_cipher_fi has 4 failures.
  - 92.aes_cipher_fi.20381575331746052092548670436098007028232065246278592753909218470189463639959
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/92.aes_cipher_fi/latest/run.log
```
  Job ID: smart:8b52afbd-cc94-462b-a66e-bb2452dbd941
```
  - 93.aes_cipher_fi.115370682171239569028784778093965320933678342113342773654928813504085285436194
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/93.aes_cipher_fi/latest/run.log
```
  Job ID: smart:9b973da2-20a9-4736-bad5-c6146a74852c
```
  - ... and 2 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 7 failures:

Test aes_stress_all_with_rand_reset has 7 failures.

1.aes_stress_all_with_rand_reset.99777306791920188337640760795408486088354384786524299849346759661873335999272
Line 525, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 5801389507 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 5801389507 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.aes_stress_all_with_rand_reset.68100251715489062771630584016861631219060448712620587058782720170597464219633
Line 456, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 755044670 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 755044670 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 5 failures:
- Test aes_cipher_fi has 5 failures.
  - 129.aes_cipher_fi.39030127341817708373949833995539573894368932830280920684412015173546928833065
    Line 324, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/129.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10014754808 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10014754808 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 141.aes_cipher_fi.14545539737789843050924515494494071036996173027481009031625207067821893347990
    Line 326, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/141.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10007835559 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10007835559 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 3 failures:
- Test aes_core_fi has 3 failures.
  - 29.aes_core_fi.79299458907438316396373559128431476584109001960032499749014090664415277587108
    Line 320, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/29.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10010486229 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10010486229 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 42.aes_core_fi.23873890297896341334757170874003979526647840667194245347904916980658712946524
    Line 326, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/42.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10088491103 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10088491103 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 2 failures:

Test aes_stress_all_with_rand_reset has 2 failures.

0.aes_stress_all_with_rand_reset.95282521241298247288396516953141269124605989506592639336528145523272591243770
Line 1152, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2201150572 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 2201150572 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

8.aes_stress_all_with_rand_reset.98835574846839412836825742330720029508557145964387448451315992178395011628299
Line 1287, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/8.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1203862102 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1203862102 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_vseq.sv:840) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 2.aes_stress_all_with_rand_reset.114865332564974770858249366604762196962534024653686412366772673118168613059707
    Line 473, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 653355994 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 653355994 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_control_fi has 1 failures.
  - 74.aes_control_fi.25015043038882876108953505644935177297573977273505509177977516294263894833476
    Line 313, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/74.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10007405258 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10007405258 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```