AES/MASKED Simulation Results

Saturday July 20 2024 23:02:34 UTC

GitHub Revision: `e971cd9798`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 85433431889345478971181747401055702269263498582281270185582621732035232392187

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	9.000s	87.102us	1	1	100.00
V1	smoke	aes_smoke	13.000s	235.958us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	64.903us	5	5	100.00
V1	csr_rw	aes_csr_rw	3.000s	146.395us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	13.000s	2.667ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	6.000s	279.745us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	4.000s	102.207us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	3.000s	146.395us	20	20	100.00
		aes_csr_aliasing	6.000s	279.745us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	13.000s	235.958us	50	50	100.00
		aes_config_error	23.000s	766.746us	50	50	100.00
		aes_stress	1.133m	2.383ms	50	50	100.00
V2	key_length	aes_smoke	13.000s	235.958us	50	50	100.00
		aes_config_error	23.000s	766.746us	50	50	100.00
		aes_stress	1.133m	2.383ms	50	50	100.00
V2	back2back	aes_stress	1.133m	2.383ms	50	50	100.00
		aes_b2b	43.000s	1.217ms	50	50	100.00
V2	backpressure	aes_stress	1.133m	2.383ms	50	50	100.00
V2	multi_message	aes_smoke	13.000s	235.958us	50	50	100.00
		aes_config_error	23.000s	766.746us	50	50	100.00
		aes_stress	1.133m	2.383ms	50	50	100.00
		aes_alert_reset	29.000s	2.872ms	50	50	100.00
V2	failure_test	aes_man_cfg_err	14.000s	121.518us	50	50	100.00
		aes_config_error	23.000s	766.746us	50	50	100.00
		aes_alert_reset	29.000s	2.872ms	50	50	100.00
V2	trigger_clear_test	aes_clear	23.000s	1.328ms	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	12.000s	644.197us	1	1	100.00
V2	reset_recovery	aes_alert_reset	29.000s	2.872ms	50	50	100.00
V2	stress	aes_stress	1.133m	2.383ms	50	50	100.00
V2	sideload	aes_stress	1.133m	2.383ms	50	50	100.00
		aes_sideload	38.000s	1.404ms	50	50	100.00
V2	deinitialization	aes_deinit	19.000s	80.797us	50	50	100.00
V2	stress_all	aes_stress_all	1.367m	3.623ms	10	10	100.00
V2	alert_test	aes_alert_test	14.000s	397.144us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	6.000s	122.463us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	6.000s	122.463us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	64.903us	5	5	100.00
		aes_csr_rw	3.000s	146.395us	20	20	100.00
		aes_csr_aliasing	6.000s	279.745us	5	5	100.00
		aes_same_csr_outstanding	4.000s	179.704us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	64.903us	5	5	100.00
		aes_csr_rw	3.000s	146.395us	20	20	100.00
		aes_csr_aliasing	6.000s	279.745us	5	5	100.00
		aes_same_csr_outstanding	4.000s	179.704us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	23.000s	606.916us	49	50	98.00
V2S	fault_inject	aes_fi	13.000s	825.921us	48	50	96.00
		aes_control_fi	34.000s	10.166ms	287	300	95.67
		aes_cipher_fi	47.000s	10.005ms	339	350	96.86
V2S	shadow_reg_update_error	aes_shadow_reg_errors	5.000s	61.618us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	5.000s	61.618us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	5.000s	61.618us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	5.000s	61.618us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	4.000s	359.230us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	7.000s	667.043us	5	5	100.00
		aes_tl_intg_err	5.000s	443.727us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	5.000s	443.727us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	29.000s	2.872ms	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	5.000s	61.618us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	13.000s	235.958us	50	50	100.00
		aes_stress	1.133m	2.383ms	50	50	100.00
		aes_alert_reset	29.000s	2.872ms	50	50	100.00
		aes_core_fi	1.417m	10.009ms	66	70	94.29
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	5.000s	61.618us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	13.000s	77.896us	50	50	100.00
		aes_stress	1.133m	2.383ms	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	1.133m	2.383ms	50	50	100.00
		aes_sideload	38.000s	1.404ms	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	13.000s	77.896us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	13.000s	77.896us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	13.000s	77.896us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	13.000s	77.896us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	13.000s	77.896us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	1.133m	2.383ms	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	1.133m	2.383ms	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	13.000s	825.921us	48	50	96.00
V2S	sec_cm_main_fsm_redun	aes_fi	13.000s	825.921us	48	50	96.00
		aes_control_fi	34.000s	10.166ms	287	300	95.67
		aes_cipher_fi	47.000s	10.005ms	339	350	96.86
		aes_ctr_fi	17.000s	86.865us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	13.000s	825.921us	48	50	96.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	13.000s	825.921us	48	50	96.00
		aes_control_fi	34.000s	10.166ms	287	300	95.67
		aes_cipher_fi	47.000s	10.005ms	339	350	96.86
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	47.000s	10.005ms	339	350	96.86
V2S	sec_cm_ctr_fsm_sparse	aes_fi	13.000s	825.921us	48	50	96.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	13.000s	825.921us	48	50	96.00
		aes_control_fi	34.000s	10.166ms	287	300	95.67
		aes_ctr_fi	17.000s	86.865us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	13.000s	825.921us	48	50	96.00
		aes_control_fi	34.000s	10.166ms	287	300	95.67
		aes_cipher_fi	47.000s	10.005ms	339	350	96.86
		aes_ctr_fi	17.000s	86.865us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	29.000s	2.872ms	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	13.000s	825.921us	48	50	96.00
		aes_control_fi	34.000s	10.166ms	287	300	95.67
		aes_cipher_fi	47.000s	10.005ms	339	350	96.86
		aes_ctr_fi	17.000s	86.865us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	13.000s	825.921us	48	50	96.00
		aes_control_fi	34.000s	10.166ms	287	300	95.67
		aes_cipher_fi	47.000s	10.005ms	339	350	96.86
		aes_ctr_fi	17.000s	86.865us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	13.000s	825.921us	48	50	96.00
		aes_control_fi	34.000s	10.166ms	287	300	95.67
		aes_ctr_fi	17.000s	86.865us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	13.000s	825.921us	48	50	96.00
		aes_control_fi	34.000s	10.166ms	287	300	95.67
		aes_cipher_fi	47.000s	10.005ms	339	350	96.86
V2S		TOTAL			954	985	96.85
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	10.000m	20.925ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1561	1602	97.44

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	13	100.00
V2S	11	11	6	54.55
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.32	98.52	96.23	99.42	95.72	97.72	97.78	98.96	96.41

Failure Buckets

Job aes_masked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 15 failures:
- Test aes_control_fi has 11 failures.
  - 1.aes_control_fi.89789351014930475611172810488850440889363504336430823686818895228815435092771
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_control_fi/latest/run.log
```
  Job ID: smart:96e3747b-2117-47ad-a1e2-f232ff406442
```
  - 33.aes_control_fi.56352675848620514066275131486470811478982132361279293709117090509259988287174
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/33.aes_control_fi/latest/run.log
```
  Job ID: smart:6909b78c-8357-44d0-b930-515e525bc993
```
  - ... and 9 more failures.
- Test aes_cipher_fi has 4 failures.
  - 125.aes_cipher_fi.113733438246120633437691853305140935037671800969649202043868407170763752104027
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/125.aes_cipher_fi/latest/run.log
```
  Job ID: smart:6984e463-46eb-4ced-8f46-cfb354e73259
```
  - 196.aes_cipher_fi.48193772483759766854131671301331199272306225633494276282115902156627079030665
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/196.aes_cipher_fi/latest/run.log
```
  Job ID: smart:b90a44a3-a3e5-4066-8f52-fbfabaa79759
```
  - ... and 2 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 7 failures:

Test aes_stress_all_with_rand_reset has 7 failures.

0.aes_stress_all_with_rand_reset.79742337447961724059882367016563548960363993532537088225408006938319597918227
Line 1121, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 758497006 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 758497006 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.8659695532136836561841727328100874017545540376937976336375648612664386072135
Line 638, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 337400934 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 337400934 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 7 failures:
- Test aes_cipher_fi has 7 failures.
  - 134.aes_cipher_fi.60217564051941240652300862638978073857081584021829109329822585185792190665983
    Line 322, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/134.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10008591284 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10008591284 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 172.aes_cipher_fi.65692764728186359740527372014145064089019014851851378056764164004805546073674
    Line 320, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/172.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10008239182 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10008239182 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 4 failures:
- Test aes_core_fi has 4 failures.
  - 6.aes_core_fi.68887620122985967277443923957236186382369089007097767226993779431364195941971
    Line 314, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/6.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10005520988 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10005520988 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 19.aes_core_fi.83444272681569029336264881084008616254675526973833450044844187037961187926381
    Line 325, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/19.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10008877556 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10008877556 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 3 failures:

Test aes_stress_all_with_rand_reset has 3 failures.

7.aes_stress_all_with_rand_reset.36376129200588439917905755390328829553215241949845635519522458276347087846396
Line 1212, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/7.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2455762232 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 2455762232 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

8.aes_stress_all_with_rand_reset.115513798787536403910653364596228192137216871370566147742438093870647995463456
Line 1458, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/8.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2981239664 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 2981239664 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_control_fi has 2 failures.
  - 35.aes_control_fi.110616815215012801206352980363443635358599526513861318079941765842461283690155
    Line 327, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/35.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10165514473 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10165514473 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 226.aes_control_fi.35893969141691524221028539117780241937205272921196817045853837505572433654683
    Line 315, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/226.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10014213470 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10014213470 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_FATAL (aes_fi_vseq.sv:69) virtual_sequencer [aes_fi_vseq] Was Able to finish without clearing reset has 2 failures:

Test aes_fi has 2 failures.

39.aes_fi.66056934401966214991930906536608391190978429644119150704901064342708927873409
Line 17801, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/39.aes_fi/latest/run.log

  UVM_FATAL @ 155007231 ps: (aes_fi_vseq.sv:69) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.aes_fi_vseq] Was Able to finish without clearing reset
  UVM_INFO @ 155007231 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

48.aes_fi.30988898660715079667895368749163084304808984210005810228427865847252782635664
Line 40516, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/48.aes_fi/latest/run.log

  UVM_FATAL @ 177532204 ps: (aes_fi_vseq.sv:69) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.aes_fi_vseq] Was Able to finish without clearing reset
  UVM_INFO @ 177532204 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (aes_reseed_vseq.sv:40) [aes_reseed_vseq] Check failed request_seen | finished_all_msgs == *'b* (* [*] vs * [*]) has 1 failures:
- Test aes_reseed has 1 failures.
  - 9.aes_reseed.76506051266534892931851885752563777193462557604605848934096835210027752867513
    Line 3989, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/9.aes_reseed/latest/run.log
```
  UVM_FATAL @ 449099370 ps: (aes_reseed_vseq.sv:40) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed request_seen | finished_all_msgs == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 449099370 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```