AES/MASKED Simulation Results

Tuesday July 23 2024 23:02:17 UTC

GitHub Revision: `0bfa990ddc`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 18885947517810151702135064218189465175127531856323617115052940021793720055953

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	142.314us	1	1	100.00
V1	smoke	aes_smoke	22.000s	654.558us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	117.900us	5	5	100.00
V1	csr_rw	aes_csr_rw	3.000s	63.093us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	10.000s	642.666us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	505.656us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	4.000s	72.294us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	3.000s	63.093us	20	20	100.00
		aes_csr_aliasing	5.000s	505.656us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	22.000s	654.558us	50	50	100.00
		aes_config_error	12.000s	111.745us	50	50	100.00
		aes_stress	18.000s	599.087us	50	50	100.00
V2	key_length	aes_smoke	22.000s	654.558us	50	50	100.00
		aes_config_error	12.000s	111.745us	50	50	100.00
		aes_stress	18.000s	599.087us	50	50	100.00
V2	back2back	aes_stress	18.000s	599.087us	50	50	100.00
		aes_b2b	27.000s	2.330ms	50	50	100.00
V2	backpressure	aes_stress	18.000s	599.087us	50	50	100.00
V2	multi_message	aes_smoke	22.000s	654.558us	50	50	100.00
		aes_config_error	12.000s	111.745us	50	50	100.00
		aes_stress	18.000s	599.087us	50	50	100.00
		aes_alert_reset	17.000s	181.804us	50	50	100.00
V2	failure_test	aes_man_cfg_err	8.000s	67.928us	50	50	100.00
		aes_config_error	12.000s	111.745us	50	50	100.00
		aes_alert_reset	17.000s	181.804us	50	50	100.00
V2	trigger_clear_test	aes_clear	2.850m	4.878ms	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	10.000s	297.760us	1	1	100.00
V2	reset_recovery	aes_alert_reset	17.000s	181.804us	50	50	100.00
V2	stress	aes_stress	18.000s	599.087us	50	50	100.00
V2	sideload	aes_stress	18.000s	599.087us	50	50	100.00
		aes_sideload	1.050m	3.426ms	50	50	100.00
V2	deinitialization	aes_deinit	30.000s	952.525us	50	50	100.00
V2	stress_all	aes_stress_all	5.867m	10.965ms	8	10	80.00
V2	alert_test	aes_alert_test	13.000s	56.769us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	6.000s	679.398us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	6.000s	679.398us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	117.900us	5	5	100.00
		aes_csr_rw	3.000s	63.093us	20	20	100.00
		aes_csr_aliasing	5.000s	505.656us	5	5	100.00
		aes_same_csr_outstanding	4.000s	141.196us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	117.900us	5	5	100.00
		aes_csr_rw	3.000s	63.093us	20	20	100.00
		aes_csr_aliasing	5.000s	505.656us	5	5	100.00
		aes_same_csr_outstanding	4.000s	141.196us	20	20	100.00
V2		TOTAL			499	501	99.60
V2S	reseeding	aes_reseed	33.000s	1.354ms	50	50	100.00
V2S	fault_inject	aes_fi	41.000s	2.227ms	50	50	100.00
		aes_control_fi	41.000s	10.005ms	285	300	95.00
		aes_cipher_fi	47.000s	10.007ms	333	350	95.14
V2S	shadow_reg_update_error	aes_shadow_reg_errors	3.000s	82.196us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	3.000s	82.196us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	3.000s	82.196us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	3.000s	82.196us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	5.000s	387.650us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	10.000s	907.323us	5	5	100.00
		aes_tl_intg_err	7.000s	1.829ms	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	7.000s	1.829ms	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	17.000s	181.804us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	3.000s	82.196us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	22.000s	654.558us	50	50	100.00
		aes_stress	18.000s	599.087us	50	50	100.00
		aes_alert_reset	17.000s	181.804us	50	50	100.00
		aes_core_fi	25.000s	10.049ms	69	70	98.57
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	3.000s	82.196us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	9.000s	68.646us	50	50	100.00
		aes_stress	18.000s	599.087us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	18.000s	599.087us	50	50	100.00
		aes_sideload	1.050m	3.426ms	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	9.000s	68.646us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	9.000s	68.646us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	9.000s	68.646us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	9.000s	68.646us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	9.000s	68.646us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	18.000s	599.087us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	18.000s	599.087us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	41.000s	2.227ms	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	41.000s	2.227ms	50	50	100.00
		aes_control_fi	41.000s	10.005ms	285	300	95.00
		aes_cipher_fi	47.000s	10.007ms	333	350	95.14
		aes_ctr_fi	13.000s	77.446us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	41.000s	2.227ms	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	41.000s	2.227ms	50	50	100.00
		aes_control_fi	41.000s	10.005ms	285	300	95.00
		aes_cipher_fi	47.000s	10.007ms	333	350	95.14
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	47.000s	10.007ms	333	350	95.14
V2S	sec_cm_ctr_fsm_sparse	aes_fi	41.000s	2.227ms	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	41.000s	2.227ms	50	50	100.00
		aes_control_fi	41.000s	10.005ms	285	300	95.00
		aes_ctr_fi	13.000s	77.446us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	41.000s	2.227ms	50	50	100.00
		aes_control_fi	41.000s	10.005ms	285	300	95.00
		aes_cipher_fi	47.000s	10.007ms	333	350	95.14
		aes_ctr_fi	13.000s	77.446us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	17.000s	181.804us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	41.000s	2.227ms	50	50	100.00
		aes_control_fi	41.000s	10.005ms	285	300	95.00
		aes_cipher_fi	47.000s	10.007ms	333	350	95.14
		aes_ctr_fi	13.000s	77.446us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	41.000s	2.227ms	50	50	100.00
		aes_control_fi	41.000s	10.005ms	285	300	95.00
		aes_cipher_fi	47.000s	10.007ms	333	350	95.14
		aes_ctr_fi	13.000s	77.446us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	41.000s	2.227ms	50	50	100.00
		aes_control_fi	41.000s	10.005ms	285	300	95.00
		aes_ctr_fi	13.000s	77.446us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	41.000s	2.227ms	50	50	100.00
		aes_control_fi	41.000s	10.005ms	285	300	95.00
		aes_cipher_fi	47.000s	10.007ms	333	350	95.14
V2S		TOTAL			952	985	96.65
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	5.767m	10.230ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1557	1602	97.19

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	12	92.31
V2S	11	11	8	72.73
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.31	98.52	96.23	99.39	95.76	97.64	97.78	98.96	96.61

Failure Buckets

Job aes_masked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 17 failures:
- Test aes_control_fi has 12 failures.
  - 7.aes_control_fi.97962595665646195558632621653355556553474129103983689144140087998083109974673
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/7.aes_control_fi/latest/run.log
```
  Job ID: smart:37fe78b4-e526-4056-8676-3485b778c8b2
```
  - 33.aes_control_fi.52693719183327057543253859322657889477191974828620302941078003460836351886897
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/33.aes_control_fi/latest/run.log
```
  Job ID: smart:00a3565f-341a-484f-a664-4151ac17708c
```
  - ... and 10 more failures.
- Test aes_cipher_fi has 5 failures.
  - 43.aes_cipher_fi.29772495525926812389890962175231122337297944386933139952016267233664301264697
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/43.aes_cipher_fi/latest/run.log
```
  Job ID: smart:394e2a54-4903-4066-9d7a-9377c85b1d14
```
  - 45.aes_cipher_fi.94251774218597710734477050568852166161104378329726925363337560298307411921391
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/45.aes_cipher_fi/latest/run.log
```
  Job ID: smart:a904b84e-5f2c-44e7-ae32-5a06679d9631
```
  - ... and 3 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 12 failures:
- Test aes_cipher_fi has 12 failures.
  - 30.aes_cipher_fi.68272190508673310122576090520150412799744646932779868791197692933772273532488
    Line 315, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/30.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10007568810 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10007568810 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 52.aes_cipher_fi.15245604311568668549238089767518062207574647228413956784128334512958270343785
    Line 331, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/52.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10007071430 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10007071430 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 10 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 6 failures:

Test aes_stress_all_with_rand_reset has 6 failures.

0.aes_stress_all_with_rand_reset.82991721106618263845953442831444351261684356394195654920132742122951646992676
Line 1328, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1464720224 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1464720224 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.95358737811813041042183654379089940498554043454489204201053174472935923700816
Line 1226, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 4720880540 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 4720880540 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 3 failures:

Test aes_stress_all_with_rand_reset has 3 failures.

5.aes_stress_all_with_rand_reset.39980988055246509398799411155115274600387770828751763183560532314692998070571
Line 1683, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/5.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1846685386 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1846685386 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

7.aes_stress_all_with_rand_reset.81670643555601695639979533804782250561481107933338836779396654146027727118433
Line 573, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/7.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 375713199 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 375713199 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 3 failures:
- Test aes_control_fi has 3 failures.
  - 12.aes_control_fi.51341764685774749173140459308989047458934684615292670423080285807550779745844
    Line 319, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/12.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10005443170 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10005443170 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 78.aes_control_fi.38322793820398812271503411300554898263549462868217446792064972990004783350541
    Line 324, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/78.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10021507469 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10021507469 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,987): Assertion AesSecCmDataRegLocalEscDataOut has failed (* cycles, starting * PS) has 1 failures:
- Test aes_stress_all has 1 failures.
  - 0.aes_stress_all.87358659198833359670623195133420321675254883394215111900454026862502488661601
    Line 48835, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_stress_all/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,987): (time 565989194 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 565979194 PS)
  UVM_ERROR @ 565989194 ps: (aes_core.sv:987) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut
  UVM_INFO @ 565989194 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:840) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 4.aes_stress_all_with_rand_reset.22501121419914370551932818584001211196098510260507691510154112255129501334978
    Line 527, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/4.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 10229517817 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 10229517817 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,993): Assertion AesSecCmDataRegLocalEscIv has failed (* cycles, starting * PS) has 1 failures:
- Test aes_stress_all has 1 failures.
  - 5.aes_stress_all.7930606136637567157960379016780500551663255792243309692233582106228563968793
    Line 75668, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/5.aes_stress_all/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,993): (time 198526083 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 198515879 PS)
  UVM_ERROR @ 198526083 ps: (aes_core.sv:993) [ASSERT FAILED] AesSecCmDataRegLocalEscIv
  UVM_INFO @ 198526083 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 32.aes_core_fi.50858879618531307443767301238795363553023200755322751954538219200416830602050
    Line 314, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/32.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10049022448 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10049022448 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```