AES/MASKED Simulation Results

Monday July 22 2024 23:02:17 UTC

GitHub Revision: 3e0219a2c5

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 78193674045195286552709223969981662100934453993551616519215297815848091296886

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 wake_up aes_wake_up 3.000s 67.240us 1 1 100.00
V1 smoke aes_smoke 20.000s 644.827us 50 50 100.00
V1 csr_hw_reset aes_csr_hw_reset 4.000s 72.491us 5 5 100.00
V1 csr_rw aes_csr_rw 3.000s 63.204us 20 20 100.00
V1 csr_bit_bash aes_csr_bit_bash 8.000s 120.012us 5 5 100.00
V1 csr_aliasing aes_csr_aliasing 5.000s 465.202us 5 5 100.00
V1 csr_mem_rw_with_rand_reset aes_csr_mem_rw_with_rand_reset 11.000s 62.362us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr aes_csr_rw 3.000s 63.204us 20 20 100.00
aes_csr_aliasing 5.000s 465.202us 5 5 100.00
V1 TOTAL 106 106 100.00
V2 algorithm aes_smoke 20.000s 644.827us 50 50 100.00
aes_config_error 1.317m 54.513us 50 50 100.00
aes_stress 1.333m 122.730us 50 50 100.00
V2 key_length aes_smoke 20.000s 644.827us 50 50 100.00
aes_config_error 1.317m 54.513us 50 50 100.00
aes_stress 1.333m 122.730us 50 50 100.00
V2 back2back aes_stress 1.333m 122.730us 50 50 100.00
aes_b2b 45.000s 622.337us 50 50 100.00
V2 backpressure aes_stress 1.333m 122.730us 50 50 100.00
V2 multi_message aes_smoke 20.000s 644.827us 50 50 100.00
aes_config_error 1.317m 54.513us 50 50 100.00
aes_stress 1.333m 122.730us 50 50 100.00
aes_alert_reset 46.000s 138.792us 50 50 100.00
V2 failure_test aes_man_cfg_err 1.317m 73.036us 50 50 100.00
aes_config_error 1.317m 54.513us 50 50 100.00
aes_alert_reset 46.000s 138.792us 50 50 100.00
V2 trigger_clear_test aes_clear 1.233m 2.007ms 50 50 100.00
V2 nist_test_vectors aes_nist_vectors 3.217m 9.088ms 1 1 100.00
V2 reset_recovery aes_alert_reset 46.000s 138.792us 50 50 100.00
V2 stress aes_stress 1.333m 122.730us 50 50 100.00
V2 sideload aes_stress 1.333m 122.730us 50 50 100.00
aes_sideload 8.000s 1.651ms 50 50 100.00
V2 deinitialization aes_deinit 51.000s 1.743ms 50 50 100.00
V2 stress_all aes_stress_all 3.800m 6.933ms 10 10 100.00
V2 alert_test aes_alert_test 14.000s 152.336us 50 50 100.00
V2 tl_d_oob_addr_access aes_tl_errors 8.000s 472.363us 20 20 100.00
V2 tl_d_illegal_access aes_tl_errors 8.000s 472.363us 20 20 100.00
V2 tl_d_outstanding_access aes_csr_hw_reset 4.000s 72.491us 5 5 100.00
aes_csr_rw 3.000s 63.204us 20 20 100.00
aes_csr_aliasing 5.000s 465.202us 5 5 100.00
aes_same_csr_outstanding 11.000s 67.354us 20 20 100.00
V2 tl_d_partial_access aes_csr_hw_reset 4.000s 72.491us 5 5 100.00
aes_csr_rw 3.000s 63.204us 20 20 100.00
aes_csr_aliasing 5.000s 465.202us 5 5 100.00
aes_same_csr_outstanding 11.000s 67.354us 20 20 100.00
V2 TOTAL 501 501 100.00
V2S reseeding aes_reseed 5.067m 8.506ms 50 50 100.00
V2S fault_inject aes_fi 13.000s 147.335us 49 50 98.00
aes_control_fi 51.000s 10.012ms 280 300 93.33
aes_cipher_fi 31.000s 10.010ms 338 350 96.57
V2S shadow_reg_update_error aes_shadow_reg_errors 4.000s 56.818us 20 20 100.00
V2S shadow_reg_read_clear_staged_value aes_shadow_reg_errors 4.000s 56.818us 20 20 100.00
V2S shadow_reg_storage_error aes_shadow_reg_errors 4.000s 56.818us 20 20 100.00
V2S shadowed_reset_glitch aes_shadow_reg_errors 4.000s 56.818us 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw aes_shadow_reg_errors_with_csr_rw 4.000s 260.850us 20 20 100.00
V2S tl_intg_err aes_sec_cm 21.000s 1.950ms 5 5 100.00
aes_tl_intg_err 26.000s 176.423us 20 20 100.00
V2S sec_cm_bus_integrity aes_tl_intg_err 26.000s 176.423us 20 20 100.00
V2S sec_cm_lc_escalate_en_intersig_mubi aes_alert_reset 46.000s 138.792us 50 50 100.00
V2S sec_cm_main_config_shadow aes_shadow_reg_errors 4.000s 56.818us 20 20 100.00
V2S sec_cm_main_config_sparse aes_smoke 20.000s 644.827us 50 50 100.00
aes_stress 1.333m 122.730us 50 50 100.00
aes_alert_reset 46.000s 138.792us 50 50 100.00
aes_core_fi 1.733m 10.020ms 64 70 91.43
V2S sec_cm_aux_config_shadow aes_shadow_reg_errors 4.000s 56.818us 20 20 100.00
V2S sec_cm_aux_config_regwen aes_readability 21.000s 61.776us 50 50 100.00
aes_stress 1.333m 122.730us 50 50 100.00
V2S sec_cm_key_sideload aes_stress 1.333m 122.730us 50 50 100.00
aes_sideload 8.000s 1.651ms 50 50 100.00
V2S sec_cm_key_sw_unreadable aes_readability 21.000s 61.776us 50 50 100.00
V2S sec_cm_data_reg_sw_unreadable aes_readability 21.000s 61.776us 50 50 100.00
V2S sec_cm_key_sec_wipe aes_readability 21.000s 61.776us 50 50 100.00
V2S sec_cm_iv_config_sec_wipe aes_readability 21.000s 61.776us 50 50 100.00
V2S sec_cm_data_reg_sec_wipe aes_readability 21.000s 61.776us 50 50 100.00
V2S sec_cm_data_reg_key_sca aes_stress 1.333m 122.730us 50 50 100.00
V2S sec_cm_key_masking aes_stress 1.333m 122.730us 50 50 100.00
V2S sec_cm_main_fsm_sparse aes_fi 13.000s 147.335us 49 50 98.00
V2S sec_cm_main_fsm_redun aes_fi 13.000s 147.335us 49 50 98.00
aes_control_fi 51.000s 10.012ms 280 300 93.33
aes_cipher_fi 31.000s 10.010ms 338 350 96.57
aes_ctr_fi 8.000s 67.492us 47 50 94.00
V2S sec_cm_cipher_fsm_sparse aes_fi 13.000s 147.335us 49 50 98.00
V2S sec_cm_cipher_fsm_redun aes_fi 13.000s 147.335us 49 50 98.00
aes_control_fi 51.000s 10.012ms 280 300 93.33
aes_cipher_fi 31.000s 10.010ms 338 350 96.57
V2S sec_cm_cipher_ctr_redun aes_cipher_fi 31.000s 10.010ms 338 350 96.57
V2S sec_cm_ctr_fsm_sparse aes_fi 13.000s 147.335us 49 50 98.00
V2S sec_cm_ctr_fsm_redun aes_fi 13.000s 147.335us 49 50 98.00
aes_control_fi 51.000s 10.012ms 280 300 93.33
aes_ctr_fi 8.000s 67.492us 47 50 94.00
V2S sec_cm_ctrl_sparse aes_fi 13.000s 147.335us 49 50 98.00
aes_control_fi 51.000s 10.012ms 280 300 93.33
aes_cipher_fi 31.000s 10.010ms 338 350 96.57
aes_ctr_fi 8.000s 67.492us 47 50 94.00
V2S sec_cm_main_fsm_global_esc aes_alert_reset 46.000s 138.792us 50 50 100.00
V2S sec_cm_main_fsm_local_esc aes_fi 13.000s 147.335us 49 50 98.00
aes_control_fi 51.000s 10.012ms 280 300 93.33
aes_cipher_fi 31.000s 10.010ms 338 350 96.57
aes_ctr_fi 8.000s 67.492us 47 50 94.00
V2S sec_cm_cipher_fsm_local_esc aes_fi 13.000s 147.335us 49 50 98.00
aes_control_fi 51.000s 10.012ms 280 300 93.33
aes_cipher_fi 31.000s 10.010ms 338 350 96.57
aes_ctr_fi 8.000s 67.492us 47 50 94.00
V2S sec_cm_ctr_fsm_local_esc aes_fi 13.000s 147.335us 49 50 98.00
aes_control_fi 51.000s 10.012ms 280 300 93.33
aes_ctr_fi 8.000s 67.492us 47 50 94.00
V2S sec_cm_data_reg_local_esc aes_fi 13.000s 147.335us 49 50 98.00
aes_control_fi 51.000s 10.012ms 280 300 93.33
aes_cipher_fi 31.000s 10.010ms 338 350 96.57
V2S TOTAL 943 985 95.74
V3 stress_all_with_rand_reset aes_stress_all_with_rand_reset 3.783m 7.139ms 0 10 0.00
V3 TOTAL 0 10 0.00
TOTAL 1550 1602 96.75

Testplan Progress

Items Total Written Passing Progress
V1 7 7 7 100.00
V2 13 13 13 100.00
V2S 11 11 6 54.55
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
98.36 98.54 96.30 99.45 95.72 97.72 100.00 99.11 96.61

Failure Buckets

Past Results