AES/MASKED Simulation Results

Monday July 22 2024 23:02:17 UTC

GitHub Revision: `3e0219a2c5`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 78193674045195286552709223969981662100934453993551616519215297815848091296886

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	67.240us	1	1	100.00
V1	smoke	aes_smoke	20.000s	644.827us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	4.000s	72.491us	5	5	100.00
V1	csr_rw	aes_csr_rw	3.000s	63.204us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	8.000s	120.012us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	465.202us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	11.000s	62.362us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	3.000s	63.204us	20	20	100.00
		aes_csr_aliasing	5.000s	465.202us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	20.000s	644.827us	50	50	100.00
		aes_config_error	1.317m	54.513us	50	50	100.00
		aes_stress	1.333m	122.730us	50	50	100.00
V2	key_length	aes_smoke	20.000s	644.827us	50	50	100.00
		aes_config_error	1.317m	54.513us	50	50	100.00
		aes_stress	1.333m	122.730us	50	50	100.00
V2	back2back	aes_stress	1.333m	122.730us	50	50	100.00
		aes_b2b	45.000s	622.337us	50	50	100.00
V2	backpressure	aes_stress	1.333m	122.730us	50	50	100.00
V2	multi_message	aes_smoke	20.000s	644.827us	50	50	100.00
		aes_config_error	1.317m	54.513us	50	50	100.00
		aes_stress	1.333m	122.730us	50	50	100.00
		aes_alert_reset	46.000s	138.792us	50	50	100.00
V2	failure_test	aes_man_cfg_err	1.317m	73.036us	50	50	100.00
		aes_config_error	1.317m	54.513us	50	50	100.00
		aes_alert_reset	46.000s	138.792us	50	50	100.00
V2	trigger_clear_test	aes_clear	1.233m	2.007ms	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	3.217m	9.088ms	1	1	100.00
V2	reset_recovery	aes_alert_reset	46.000s	138.792us	50	50	100.00
V2	stress	aes_stress	1.333m	122.730us	50	50	100.00
V2	sideload	aes_stress	1.333m	122.730us	50	50	100.00
		aes_sideload	8.000s	1.651ms	50	50	100.00
V2	deinitialization	aes_deinit	51.000s	1.743ms	50	50	100.00
V2	stress_all	aes_stress_all	3.800m	6.933ms	10	10	100.00
V2	alert_test	aes_alert_test	14.000s	152.336us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	8.000s	472.363us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	8.000s	472.363us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	4.000s	72.491us	5	5	100.00
		aes_csr_rw	3.000s	63.204us	20	20	100.00
		aes_csr_aliasing	5.000s	465.202us	5	5	100.00
		aes_same_csr_outstanding	11.000s	67.354us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	4.000s	72.491us	5	5	100.00
		aes_csr_rw	3.000s	63.204us	20	20	100.00
		aes_csr_aliasing	5.000s	465.202us	5	5	100.00
		aes_same_csr_outstanding	11.000s	67.354us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	5.067m	8.506ms	50	50	100.00
V2S	fault_inject	aes_fi	13.000s	147.335us	49	50	98.00
		aes_control_fi	51.000s	10.012ms	280	300	93.33
		aes_cipher_fi	31.000s	10.010ms	338	350	96.57
V2S	shadow_reg_update_error	aes_shadow_reg_errors	4.000s	56.818us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	4.000s	56.818us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	4.000s	56.818us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	4.000s	56.818us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	4.000s	260.850us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	21.000s	1.950ms	5	5	100.00
		aes_tl_intg_err	26.000s	176.423us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	26.000s	176.423us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	46.000s	138.792us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	4.000s	56.818us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	20.000s	644.827us	50	50	100.00
		aes_stress	1.333m	122.730us	50	50	100.00
		aes_alert_reset	46.000s	138.792us	50	50	100.00
		aes_core_fi	1.733m	10.020ms	64	70	91.43
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	4.000s	56.818us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	21.000s	61.776us	50	50	100.00
		aes_stress	1.333m	122.730us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	1.333m	122.730us	50	50	100.00
		aes_sideload	8.000s	1.651ms	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	21.000s	61.776us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	21.000s	61.776us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	21.000s	61.776us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	21.000s	61.776us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	21.000s	61.776us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	1.333m	122.730us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	1.333m	122.730us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	13.000s	147.335us	49	50	98.00
V2S	sec_cm_main_fsm_redun	aes_fi	13.000s	147.335us	49	50	98.00
		aes_control_fi	51.000s	10.012ms	280	300	93.33
		aes_cipher_fi	31.000s	10.010ms	338	350	96.57
		aes_ctr_fi	8.000s	67.492us	47	50	94.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	13.000s	147.335us	49	50	98.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	13.000s	147.335us	49	50	98.00
		aes_control_fi	51.000s	10.012ms	280	300	93.33
		aes_cipher_fi	31.000s	10.010ms	338	350	96.57
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	31.000s	10.010ms	338	350	96.57
V2S	sec_cm_ctr_fsm_sparse	aes_fi	13.000s	147.335us	49	50	98.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	13.000s	147.335us	49	50	98.00
		aes_control_fi	51.000s	10.012ms	280	300	93.33
		aes_ctr_fi	8.000s	67.492us	47	50	94.00
V2S	sec_cm_ctrl_sparse	aes_fi	13.000s	147.335us	49	50	98.00
		aes_control_fi	51.000s	10.012ms	280	300	93.33
		aes_cipher_fi	31.000s	10.010ms	338	350	96.57
		aes_ctr_fi	8.000s	67.492us	47	50	94.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	46.000s	138.792us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	13.000s	147.335us	49	50	98.00
		aes_control_fi	51.000s	10.012ms	280	300	93.33
		aes_cipher_fi	31.000s	10.010ms	338	350	96.57
		aes_ctr_fi	8.000s	67.492us	47	50	94.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	13.000s	147.335us	49	50	98.00
		aes_control_fi	51.000s	10.012ms	280	300	93.33
		aes_cipher_fi	31.000s	10.010ms	338	350	96.57
		aes_ctr_fi	8.000s	67.492us	47	50	94.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	13.000s	147.335us	49	50	98.00
		aes_control_fi	51.000s	10.012ms	280	300	93.33
		aes_ctr_fi	8.000s	67.492us	47	50	94.00
V2S	sec_cm_data_reg_local_esc	aes_fi	13.000s	147.335us	49	50	98.00
		aes_control_fi	51.000s	10.012ms	280	300	93.33
		aes_cipher_fi	31.000s	10.010ms	338	350	96.57
V2S		TOTAL			943	985	95.74
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	3.783m	7.139ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1550	1602	96.75

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	13	100.00
V2S	11	11	6	54.55
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.36	98.54	96.30	99.45	95.72	97.72	100.00	99.11	96.61

Failure Buckets

Job aes_masked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 28 failures:
- Test aes_cipher_fi has 10 failures.
  - 4.aes_cipher_fi.111468541112999703826637958271904431668558698684593714166115062869377710966257
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/4.aes_cipher_fi/latest/run.log
```
  Job ID: smart:7fc3ea03-c27b-43f2-8c52-218f1b893953
```
  - 19.aes_cipher_fi.18812607208274911316847376193856501760009342699528472739502260556581608339263
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/19.aes_cipher_fi/latest/run.log
```
  Job ID: smart:bf230dab-cf97-4d8c-9580-6d96ae9378a9
```
  - ... and 8 more failures.
- Test aes_control_fi has 15 failures.
  - 28.aes_control_fi.8986280476155383955447968314538206691128609060989569502189984306039838122816
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/28.aes_control_fi/latest/run.log
```
  Job ID: smart:c193715f-d582-4d54-bc56-c502d53c2067
```
  - 61.aes_control_fi.14901147269748798765433633842288241050244383412166779994934812624258412273596
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/61.aes_control_fi/latest/run.log
```
  Job ID: smart:92ff5063-7975-4212-9469-a4a693b3dda8
```
  - ... and 13 more failures.
- Test aes_ctr_fi has 3 failures.
  - 28.aes_ctr_fi.31071703387111171848860479222185269631141399915548362830732791156463681324917
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/28.aes_ctr_fi/latest/run.log
```
  Job ID: smart:a7213087-d966-4536-ade4-0a3433a5caaf
```
  - 29.aes_ctr_fi.43068955059822901281842622935991023034235100951367496681072330773729440741255
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/29.aes_ctr_fi/latest/run.log
```
  Job ID: smart:3d0c946f-efec-4f74-b961-fd52a7f7b536
```
  - ... and 1 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 6 failures:

Test aes_stress_all_with_rand_reset has 6 failures.

0.aes_stress_all_with_rand_reset.65752198375567506716500188456278719545337683697651828912971237626486230467029
Line 476, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 130121174 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 130121174 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.aes_stress_all_with_rand_reset.82512348153668883470155283688646907490842657955188580086286194317102385471254
Line 579, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 303618432 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 303618432 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 6 failures:
- Test aes_core_fi has 6 failures.
  - 1.aes_core_fi.108755320640325629778163232847182146390687974031018481372522212998065629224710
    Line 324, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10020219233 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10020219233 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 39.aes_core_fi.110039076656451847117431698815287066618675633602543791268569506527406750173728
    Line 320, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/39.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10008934178 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10008934178 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 5 failures:
- Test aes_control_fi has 5 failures.
  - 5.aes_control_fi.10871810131336697270467978542381159127203761191562817151653719572297799591503
    Line 315, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/5.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10010023451 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10010023451 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 82.aes_control_fi.35782622550082235937427335365940577534234714990796017955347341086772087344229
    Line 321, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/82.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10006564028 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006564028 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 4 failures:

Test aes_stress_all_with_rand_reset has 4 failures.

1.aes_stress_all_with_rand_reset.56236195839216744270174300970059026297027808813396709201781750879026256005564
Line 891, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2502268153 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 2502268153 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.aes_stress_all_with_rand_reset.4758404670033210846828290332768797077588707828323754842555400148052930760526
Line 949, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2062857660 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 2062857660 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_cipher_fi has 2 failures.
  - 167.aes_cipher_fi.51846204746846016031218314497401142919536108107147411766500595846750694388658
    Line 320, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/167.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10009810891 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10009810891 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 195.aes_cipher_fi.33284467469955622431525673310950055540609873675198402293985199582987792691281
    Line 314, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/195.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10033657438 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10033657438 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_fi_vseq.sv:69) virtual_sequencer [aes_fi_vseq] Was Able to finish without clearing reset has 1 failures:
- Test aes_fi has 1 failures.
  - 4.aes_fi.56487186419756264248469797107673111714700784459791046764293414143441871756227
    Line 66858, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/4.aes_fi/latest/run.log
```
  UVM_FATAL @ 147334787 ps: (aes_fi_vseq.sv:69) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.aes_fi_vseq] Was Able to finish without clearing reset
  UVM_INFO @ 147334787 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```