AES/MASKED Simulation Results

Wednesday July 24 2024 23:04:46 UTC

GitHub Revision: `e439226b6c`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 80778109121175195808319778278610424989650974127729484509360263424111433728567

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	87.321us	1	1	100.00
V1	smoke	aes_smoke	16.000s	760.359us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	69.726us	5	5	100.00
V1	csr_rw	aes_csr_rw	5.000s	52.780us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	10.000s	1.200ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	1.341ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	4.000s	108.021us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	5.000s	52.780us	20	20	100.00
		aes_csr_aliasing	5.000s	1.341ms	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	16.000s	760.359us	50	50	100.00
		aes_config_error	19.000s	103.007us	50	50	100.00
		aes_stress	16.000s	498.875us	50	50	100.00
V2	key_length	aes_smoke	16.000s	760.359us	50	50	100.00
		aes_config_error	19.000s	103.007us	50	50	100.00
		aes_stress	16.000s	498.875us	50	50	100.00
V2	back2back	aes_stress	16.000s	498.875us	50	50	100.00
		aes_b2b	34.000s	454.506us	50	50	100.00
V2	backpressure	aes_stress	16.000s	498.875us	50	50	100.00
V2	multi_message	aes_smoke	16.000s	760.359us	50	50	100.00
		aes_config_error	19.000s	103.007us	50	50	100.00
		aes_stress	16.000s	498.875us	50	50	100.00
		aes_alert_reset	12.000s	765.529us	50	50	100.00
V2	failure_test	aes_man_cfg_err	14.000s	269.605us	50	50	100.00
		aes_config_error	19.000s	103.007us	50	50	100.00
		aes_alert_reset	12.000s	765.529us	50	50	100.00
V2	trigger_clear_test	aes_clear	1.050m	2.071ms	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	13.000s	752.284us	1	1	100.00
V2	reset_recovery	aes_alert_reset	12.000s	765.529us	50	50	100.00
V2	stress	aes_stress	16.000s	498.875us	50	50	100.00
V2	sideload	aes_stress	16.000s	498.875us	50	50	100.00
		aes_sideload	29.000s	967.415us	50	50	100.00
V2	deinitialization	aes_deinit	28.000s	1.863ms	50	50	100.00
V2	stress_all	aes_stress_all	1.400m	1.092ms	10	10	100.00
V2	alert_test	aes_alert_test	11.000s	64.568us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	6.000s	148.684us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	6.000s	148.684us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	69.726us	5	5	100.00
		aes_csr_rw	5.000s	52.780us	20	20	100.00
		aes_csr_aliasing	5.000s	1.341ms	5	5	100.00
		aes_same_csr_outstanding	5.000s	372.449us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	69.726us	5	5	100.00
		aes_csr_rw	5.000s	52.780us	20	20	100.00
		aes_csr_aliasing	5.000s	1.341ms	5	5	100.00
		aes_same_csr_outstanding	5.000s	372.449us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	19.000s	833.006us	50	50	100.00
V2S	fault_inject	aes_fi	56.000s	2.187ms	47	50	94.00
		aes_control_fi	50.000s	10.121ms	284	300	94.67
		aes_cipher_fi	48.000s	10.004ms	339	350	96.86
V2S	shadow_reg_update_error	aes_shadow_reg_errors	4.000s	242.109us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	4.000s	242.109us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	4.000s	242.109us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	4.000s	242.109us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	5.000s	96.916us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	9.000s	1.212ms	5	5	100.00
		aes_tl_intg_err	5.000s	633.329us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	5.000s	633.329us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	12.000s	765.529us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	4.000s	242.109us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	16.000s	760.359us	50	50	100.00
		aes_stress	16.000s	498.875us	50	50	100.00
		aes_alert_reset	12.000s	765.529us	50	50	100.00
		aes_core_fi	43.000s	10.083ms	69	70	98.57
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	4.000s	242.109us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	9.000s	57.297us	50	50	100.00
		aes_stress	16.000s	498.875us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	16.000s	498.875us	50	50	100.00
		aes_sideload	29.000s	967.415us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	9.000s	57.297us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	9.000s	57.297us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	9.000s	57.297us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	9.000s	57.297us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	9.000s	57.297us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	16.000s	498.875us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	16.000s	498.875us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	56.000s	2.187ms	47	50	94.00
V2S	sec_cm_main_fsm_redun	aes_fi	56.000s	2.187ms	47	50	94.00
		aes_control_fi	50.000s	10.121ms	284	300	94.67
		aes_cipher_fi	48.000s	10.004ms	339	350	96.86
		aes_ctr_fi	27.000s	946.202us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	56.000s	2.187ms	47	50	94.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	56.000s	2.187ms	47	50	94.00
		aes_control_fi	50.000s	10.121ms	284	300	94.67
		aes_cipher_fi	48.000s	10.004ms	339	350	96.86
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	48.000s	10.004ms	339	350	96.86
V2S	sec_cm_ctr_fsm_sparse	aes_fi	56.000s	2.187ms	47	50	94.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	56.000s	2.187ms	47	50	94.00
		aes_control_fi	50.000s	10.121ms	284	300	94.67
		aes_ctr_fi	27.000s	946.202us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	56.000s	2.187ms	47	50	94.00
		aes_control_fi	50.000s	10.121ms	284	300	94.67
		aes_cipher_fi	48.000s	10.004ms	339	350	96.86
		aes_ctr_fi	27.000s	946.202us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	12.000s	765.529us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	56.000s	2.187ms	47	50	94.00
		aes_control_fi	50.000s	10.121ms	284	300	94.67
		aes_cipher_fi	48.000s	10.004ms	339	350	96.86
		aes_ctr_fi	27.000s	946.202us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	56.000s	2.187ms	47	50	94.00
		aes_control_fi	50.000s	10.121ms	284	300	94.67
		aes_cipher_fi	48.000s	10.004ms	339	350	96.86
		aes_ctr_fi	27.000s	946.202us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	56.000s	2.187ms	47	50	94.00
		aes_control_fi	50.000s	10.121ms	284	300	94.67
		aes_ctr_fi	27.000s	946.202us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	56.000s	2.187ms	47	50	94.00
		aes_control_fi	50.000s	10.121ms	284	300	94.67
		aes_cipher_fi	48.000s	10.004ms	339	350	96.86
V2S		TOTAL			954	985	96.85
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	9.100m	31.781ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1561	1602	97.44

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	13	100.00
V2S	11	11	7	63.64
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.33	98.54	96.28	99.43	95.78	97.64	97.78	98.96	96.21

Failure Buckets

Job aes_masked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 15 failures:
- Test aes_control_fi has 12 failures.
  - 5.aes_control_fi.112113642971483056021471493571111700757424545279881007876609239866289015107186
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/5.aes_control_fi/latest/run.log
```
  Job ID: smart:0d47683d-6b19-46a1-8aaf-1a5698f400bc
```
  - 44.aes_control_fi.2765446940500955134836432202889511542329928499564078033317123481221273249680
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/44.aes_control_fi/latest/run.log
```
  Job ID: smart:6e2b321b-2836-4521-bb77-2f7ef0e8f441
```
  - ... and 10 more failures.
- Test aes_cipher_fi has 3 failures.
  - 25.aes_cipher_fi.35506703618193166584102019089219841241482968173771823516376603939569154579130
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/25.aes_cipher_fi/latest/run.log
```
  Job ID: smart:9da21d9e-1cb8-4038-b728-18fba3b5b7b3
```
  - 74.aes_cipher_fi.40409654236076844355507894214263281138349013952441793695778029628838180615536
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/74.aes_cipher_fi/latest/run.log
```
  Job ID: smart:f717a0c1-e6dc-4bd3-bd27-3ceaa4f69722
```
  - ... and 1 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 8 failures:
- Test aes_cipher_fi has 8 failures.
  - 20.aes_cipher_fi.66624603052708946149188295044632915282741377118097789995397872386044647965943
    Line 324, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/20.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10008577649 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10008577649 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 32.aes_cipher_fi.75946742572290662698472366526511038180684279549342335085395255429657657944599
    Line 323, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/32.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10018502289 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10018502289 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 6 failures:

Test aes_stress_all_with_rand_reset has 6 failures.

0.aes_stress_all_with_rand_reset.114913176745094358522891114400799930721563932949799299710420509595431285167500
Line 536, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1657479745 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1657479745 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.aes_stress_all_with_rand_reset.54399382908461653645703903308104773136255115786290921042121000010409759506769
Line 861, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 374367999 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 374367999 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 4 failures:

Test aes_stress_all_with_rand_reset has 4 failures.

1.aes_stress_all_with_rand_reset.3000975979214019186808590176472696385767835169794808216419400757069447376749
Line 699, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 537061529 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 537061529 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.aes_stress_all_with_rand_reset.74016558384246011733089348942667807827670680137495067912099542697979550513667
Line 1382, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/4.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2841858914 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 2841858914 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 4 failures:
- Test aes_control_fi has 4 failures.
  - 4.aes_control_fi.92384439946351491119250031169986474047724257752615101427420221507899777325388
    Line 323, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/4.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10012868205 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10012868205 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 249.aes_control_fi.57781274706933516708249947549595034121792466786802582315372881234701857417426
    Line 318, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/249.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10121413701 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10121413701 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.

UVM_FATAL (aes_fi_vseq.sv:69) virtual_sequencer [aes_fi_vseq] Was Able to finish without clearing reset has 2 failures:

Test aes_fi has 2 failures.

17.aes_fi.11703545998774829750440180536777416325122598092623960930835127797931082912225
Line 18579, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/17.aes_fi/latest/run.log

  UVM_FATAL @ 164665027 ps: (aes_fi_vseq.sv:69) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.aes_fi_vseq] Was Able to finish without clearing reset
  UVM_INFO @ 164665027 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

49.aes_fi.7655639443178167058796735996158253080114810221543119112237997826291155447980
Line 16318, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/49.aes_fi/latest/run.log

  UVM_FATAL @ 126375659 ps: (aes_fi_vseq.sv:69) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.aes_fi_vseq] Was Able to finish without clearing reset
  UVM_INFO @ 126375659 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,993): Assertion AesSecCmDataRegLocalEscIv has failed (* cycles, starting * PS) has 1 failures:
- Test aes_fi has 1 failures.
  - 36.aes_fi.71515617571363756229496733063264118258905679867809450210593454285781822973765
    Line 1286, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/36.aes_fi/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,993): (time 139519026 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 139376169 PS)
  UVM_ERROR @ 139519026 ps: (aes_core.sv:993) [ASSERT FAILED] AesSecCmDataRegLocalEscIv
  UVM_INFO @ 139519026 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 63.aes_core_fi.83307312572848489935915106712181007613755262813327030995304334632996813265287
    Line 320, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/63.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10082868221 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10082868221 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```