AES/MASKED Simulation Results

Sunday July 21 2024 23:02:06 UTC

GitHub Revision: `e971cd9798`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 60538554475599760039478308558126864941531727393021608909386829062452482962039

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	67.156us	1	1	100.00
V1	smoke	aes_smoke	15.000s	175.721us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	64.417us	5	5	100.00
V1	csr_rw	aes_csr_rw	3.000s	101.150us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	10.000s	2.308ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	852.621us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	4.000s	58.974us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	3.000s	101.150us	20	20	100.00
		aes_csr_aliasing	5.000s	852.621us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	15.000s	175.721us	50	50	100.00
		aes_config_error	16.000s	846.200us	50	50	100.00
		aes_stress	25.000s	784.453us	50	50	100.00
V2	key_length	aes_smoke	15.000s	175.721us	50	50	100.00
		aes_config_error	16.000s	846.200us	50	50	100.00
		aes_stress	25.000s	784.453us	50	50	100.00
V2	back2back	aes_stress	25.000s	784.453us	50	50	100.00
		aes_b2b	50.000s	1.053ms	50	50	100.00
V2	backpressure	aes_stress	25.000s	784.453us	50	50	100.00
V2	multi_message	aes_smoke	15.000s	175.721us	50	50	100.00
		aes_config_error	16.000s	846.200us	50	50	100.00
		aes_stress	25.000s	784.453us	50	50	100.00
		aes_alert_reset	19.000s	282.696us	50	50	100.00
V2	failure_test	aes_man_cfg_err	14.000s	259.850us	50	50	100.00
		aes_config_error	16.000s	846.200us	50	50	100.00
		aes_alert_reset	19.000s	282.696us	50	50	100.00
V2	trigger_clear_test	aes_clear	18.000s	279.548us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	10.000s	578.753us	1	1	100.00
V2	reset_recovery	aes_alert_reset	19.000s	282.696us	50	50	100.00
V2	stress	aes_stress	25.000s	784.453us	50	50	100.00
V2	sideload	aes_stress	25.000s	784.453us	50	50	100.00
		aes_sideload	15.000s	899.323us	50	50	100.00
V2	deinitialization	aes_deinit	28.000s	697.588us	50	50	100.00
V2	stress_all	aes_stress_all	1.467m	4.209ms	10	10	100.00
V2	alert_test	aes_alert_test	18.000s	53.697us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	6.000s	708.387us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	6.000s	708.387us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	64.417us	5	5	100.00
		aes_csr_rw	3.000s	101.150us	20	20	100.00
		aes_csr_aliasing	5.000s	852.621us	5	5	100.00
		aes_same_csr_outstanding	4.000s	122.817us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	64.417us	5	5	100.00
		aes_csr_rw	3.000s	101.150us	20	20	100.00
		aes_csr_aliasing	5.000s	852.621us	5	5	100.00
		aes_same_csr_outstanding	4.000s	122.817us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	27.000s	933.923us	49	50	98.00
V2S	fault_inject	aes_fi	26.000s	2.243ms	49	50	98.00
		aes_control_fi	49.000s	10.011ms	279	300	93.00
		aes_cipher_fi	48.000s	10.006ms	338	350	96.57
V2S	shadow_reg_update_error	aes_shadow_reg_errors	3.000s	63.749us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	3.000s	63.749us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	3.000s	63.749us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	3.000s	63.749us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	4.000s	123.589us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	11.000s	952.344us	5	5	100.00
		aes_tl_intg_err	5.000s	200.873us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	5.000s	200.873us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	19.000s	282.696us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	3.000s	63.749us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	15.000s	175.721us	50	50	100.00
		aes_stress	25.000s	784.453us	50	50	100.00
		aes_alert_reset	19.000s	282.696us	50	50	100.00
		aes_core_fi	47.000s	10.019ms	69	70	98.57
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	3.000s	63.749us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	13.000s	72.570us	50	50	100.00
		aes_stress	25.000s	784.453us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	25.000s	784.453us	50	50	100.00
		aes_sideload	15.000s	899.323us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	13.000s	72.570us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	13.000s	72.570us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	13.000s	72.570us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	13.000s	72.570us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	13.000s	72.570us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	25.000s	784.453us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	25.000s	784.453us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	26.000s	2.243ms	49	50	98.00
V2S	sec_cm_main_fsm_redun	aes_fi	26.000s	2.243ms	49	50	98.00
		aes_control_fi	49.000s	10.011ms	279	300	93.00
		aes_cipher_fi	48.000s	10.006ms	338	350	96.57
		aes_ctr_fi	10.000s	441.268us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	26.000s	2.243ms	49	50	98.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	26.000s	2.243ms	49	50	98.00
		aes_control_fi	49.000s	10.011ms	279	300	93.00
		aes_cipher_fi	48.000s	10.006ms	338	350	96.57
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	48.000s	10.006ms	338	350	96.57
V2S	sec_cm_ctr_fsm_sparse	aes_fi	26.000s	2.243ms	49	50	98.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	26.000s	2.243ms	49	50	98.00
		aes_control_fi	49.000s	10.011ms	279	300	93.00
		aes_ctr_fi	10.000s	441.268us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	26.000s	2.243ms	49	50	98.00
		aes_control_fi	49.000s	10.011ms	279	300	93.00
		aes_cipher_fi	48.000s	10.006ms	338	350	96.57
		aes_ctr_fi	10.000s	441.268us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	19.000s	282.696us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	26.000s	2.243ms	49	50	98.00
		aes_control_fi	49.000s	10.011ms	279	300	93.00
		aes_cipher_fi	48.000s	10.006ms	338	350	96.57
		aes_ctr_fi	10.000s	441.268us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	26.000s	2.243ms	49	50	98.00
		aes_control_fi	49.000s	10.011ms	279	300	93.00
		aes_cipher_fi	48.000s	10.006ms	338	350	96.57
		aes_ctr_fi	10.000s	441.268us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	26.000s	2.243ms	49	50	98.00
		aes_control_fi	49.000s	10.011ms	279	300	93.00
		aes_ctr_fi	10.000s	441.268us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	26.000s	2.243ms	49	50	98.00
		aes_control_fi	49.000s	10.011ms	279	300	93.00
		aes_cipher_fi	48.000s	10.006ms	338	350	96.57
V2S		TOTAL			949	985	96.35
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	5.450m	130.730ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1556	1602	97.13

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	13	100.00
V2S	11	11	6	54.55
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.33	98.54	96.28	99.43	95.74	97.64	97.78	98.96	96.61

Failure Buckets

Job aes_masked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 14 failures:
- Test aes_cipher_fi has 3 failures.
  - 14.aes_cipher_fi.67341731298817842625490175100199819711692619561409365136680223206383673718926
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/14.aes_cipher_fi/latest/run.log
```
  Job ID: smart:b205908a-88c0-49aa-89b3-e66613fcdc90
```
  - 104.aes_cipher_fi.16740921934242988335076162484725236995445259200182172984817878752564594986512
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/104.aes_cipher_fi/latest/run.log
```
  Job ID: smart:3be58418-d457-477a-a9d2-fe2bb8892930
```
  - ... and 1 more failures.
- Test aes_control_fi has 11 failures.
  - 20.aes_control_fi.78775521001007924240974158116372148428764700247488922792219616931399725980829
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/20.aes_control_fi/latest/run.log
```
  Job ID: smart:7abc42b8-f727-4893-9a2e-9ad4018dc273
```
  - 29.aes_control_fi.71646407706032490011101208143811857292259143175442443150191048246145255190315
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/29.aes_control_fi/latest/run.log
```
  Job ID: smart:26d38b5d-8c1c-48d2-9126-794f7bfae515
```
  - ... and 9 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 10 failures:
- Test aes_control_fi has 10 failures.
  - 5.aes_control_fi.86210145954135991261339089642349192227971622706368482000309833517713575104786
    Line 325, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/5.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10031095675 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10031095675 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 24.aes_control_fi.44887168291959955256550770999092804850582582736339164865280831875164780434312
    Line 323, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/24.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10016017021 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10016017021 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 8 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 9 failures:
- Test aes_cipher_fi has 9 failures.
  - 2.aes_cipher_fi.30672174834016958332128317738177955211214639916942830235751842170904338886168
    Line 313, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/2.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10005793017 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10005793017 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 65.aes_cipher_fi.48339263170103144205712861581851696398975966051652417785256078478067847939352
    Line 319, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/65.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10037304540 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10037304540 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 7 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 7 failures:

Test aes_stress_all_with_rand_reset has 7 failures.

0.aes_stress_all_with_rand_reset.78401121788044154051936575175148269243627939549116459186249692289278139230536
Line 630, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1870207998 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1870207998 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.68599688378760128248830661833070937822799863266035071234524333797814201845549
Line 904, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 14334061572 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 14334061572 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 3 failures:

Test aes_stress_all_with_rand_reset has 3 failures.

3.aes_stress_all_with_rand_reset.91817628982795948958079187900750317704910054473545843535442386200153309767613
Line 738, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 594772567 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 594772567 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.aes_stress_all_with_rand_reset.25534393526166963088898097106006279429237947966768315398548053572669090546936
Line 685, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/5.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 575055788 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 575055788 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,993): Assertion AesSecCmDataRegLocalEscIv has failed (* cycles, starting * PS) has 1 failures:
- Test aes_fi has 1 failures.
  - 44.aes_fi.30576286614850453975136320393892865561983171383294839278230283434013818603605
    Line 888, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/44.aes_fi/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,993): (time 41886931 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 41845264 PS)
  UVM_ERROR @  41886931 ps: (aes_core.sv:993) [ASSERT FAILED] AesSecCmDataRegLocalEscIv
  UVM_INFO @  41886931 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_reseed_vseq.sv:40) [aes_reseed_vseq] Check failed request_seen | finished_all_msgs == *'b* (* [*] vs * [*]) has 1 failures:
- Test aes_reseed has 1 failures.
  - 45.aes_reseed.34301885877090127275281740757929339600335416671667285549764060550737623493068
    Line 3888, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/45.aes_reseed/latest/run.log
```
  UVM_FATAL @ 114655106 ps: (aes_reseed_vseq.sv:40) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed request_seen | finished_all_msgs == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 114655106 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 64.aes_core_fi.2860518245879516587843793807501772259574261566416149122573269135915106222482
    Line 315, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/64.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10019342962 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10019342962 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```