AES/MASKED Simulation Results

Monday August 05 2024 23:02:13 UTC

GitHub Revision: `e4c5daa580`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 57478527486894479494471273459769404654835266620222125964939301612221385668501

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	55.256us	1	1	100.00
V1	smoke	aes_smoke	16.000s	81.161us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	56.642us	5	5	100.00
V1	csr_rw	aes_csr_rw	3.000s	75.235us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	8.000s	190.860us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	4.000s	176.281us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	4.000s	101.601us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	3.000s	75.235us	20	20	100.00
		aes_csr_aliasing	4.000s	176.281us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	16.000s	81.161us	50	50	100.00
		aes_config_error	13.000s	388.747us	50	50	100.00
		aes_stress	20.000s	609.710us	50	50	100.00
V2	key_length	aes_smoke	16.000s	81.161us	50	50	100.00
		aes_config_error	13.000s	388.747us	50	50	100.00
		aes_stress	20.000s	609.710us	50	50	100.00
V2	back2back	aes_stress	20.000s	609.710us	50	50	100.00
		aes_b2b	30.000s	1.095ms	50	50	100.00
V2	backpressure	aes_stress	20.000s	609.710us	50	50	100.00
V2	multi_message	aes_smoke	16.000s	81.161us	50	50	100.00
		aes_config_error	13.000s	388.747us	50	50	100.00
		aes_stress	20.000s	609.710us	50	50	100.00
		aes_alert_reset	34.000s	2.630ms	50	50	100.00
V2	failure_test	aes_man_cfg_err	9.000s	92.113us	50	50	100.00
		aes_config_error	13.000s	388.747us	50	50	100.00
		aes_alert_reset	34.000s	2.630ms	50	50	100.00
V2	trigger_clear_test	aes_clear	39.000s	3.378ms	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	10.000s	583.417us	1	1	100.00
V2	reset_recovery	aes_alert_reset	34.000s	2.630ms	50	50	100.00
V2	stress	aes_stress	20.000s	609.710us	50	50	100.00
V2	sideload	aes_stress	20.000s	609.710us	50	50	100.00
		aes_sideload	24.000s	1.382ms	50	50	100.00
V2	deinitialization	aes_deinit	15.000s	454.298us	50	50	100.00
V2	stress_all	aes_stress_all	8.133m	63.998ms	10	10	100.00
V2	alert_test	aes_alert_test	12.000s	84.804us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	6.000s	84.973us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	6.000s	84.973us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	56.642us	5	5	100.00
		aes_csr_rw	3.000s	75.235us	20	20	100.00
		aes_csr_aliasing	4.000s	176.281us	5	5	100.00
		aes_same_csr_outstanding	4.000s	192.583us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	56.642us	5	5	100.00
		aes_csr_rw	3.000s	75.235us	20	20	100.00
		aes_csr_aliasing	4.000s	176.281us	5	5	100.00
		aes_same_csr_outstanding	4.000s	192.583us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	17.000s	1.523ms	50	50	100.00
V2S	fault_inject	aes_fi	43.000s	2.074ms	49	50	98.00
		aes_control_fi	52.000s	10.007ms	277	300	92.33
		aes_cipher_fi	49.000s	10.008ms	335	350	95.71
V2S	shadow_reg_update_error	aes_shadow_reg_errors	3.000s	114.168us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	3.000s	114.168us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	3.000s	114.168us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	3.000s	114.168us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	4.000s	106.230us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	10.000s	928.285us	5	5	100.00
		aes_tl_intg_err	5.000s	789.797us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	5.000s	789.797us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	34.000s	2.630ms	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	3.000s	114.168us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	16.000s	81.161us	50	50	100.00
		aes_stress	20.000s	609.710us	50	50	100.00
		aes_alert_reset	34.000s	2.630ms	50	50	100.00
		aes_core_fi	22.000s	10.021ms	69	70	98.57
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	3.000s	114.168us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	18.000s	65.030us	50	50	100.00
		aes_stress	20.000s	609.710us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	20.000s	609.710us	50	50	100.00
		aes_sideload	24.000s	1.382ms	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	18.000s	65.030us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	18.000s	65.030us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	18.000s	65.030us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	18.000s	65.030us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	18.000s	65.030us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	20.000s	609.710us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	20.000s	609.710us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	43.000s	2.074ms	49	50	98.00
V2S	sec_cm_main_fsm_redun	aes_fi	43.000s	2.074ms	49	50	98.00
		aes_control_fi	52.000s	10.007ms	277	300	92.33
		aes_cipher_fi	49.000s	10.008ms	335	350	95.71
		aes_ctr_fi	13.000s	132.892us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	43.000s	2.074ms	49	50	98.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	43.000s	2.074ms	49	50	98.00
		aes_control_fi	52.000s	10.007ms	277	300	92.33
		aes_cipher_fi	49.000s	10.008ms	335	350	95.71
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	49.000s	10.008ms	335	350	95.71
V2S	sec_cm_ctr_fsm_sparse	aes_fi	43.000s	2.074ms	49	50	98.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	43.000s	2.074ms	49	50	98.00
		aes_control_fi	52.000s	10.007ms	277	300	92.33
		aes_ctr_fi	13.000s	132.892us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	43.000s	2.074ms	49	50	98.00
		aes_control_fi	52.000s	10.007ms	277	300	92.33
		aes_cipher_fi	49.000s	10.008ms	335	350	95.71
		aes_ctr_fi	13.000s	132.892us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	34.000s	2.630ms	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	43.000s	2.074ms	49	50	98.00
		aes_control_fi	52.000s	10.007ms	277	300	92.33
		aes_cipher_fi	49.000s	10.008ms	335	350	95.71
		aes_ctr_fi	13.000s	132.892us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	43.000s	2.074ms	49	50	98.00
		aes_control_fi	52.000s	10.007ms	277	300	92.33
		aes_cipher_fi	49.000s	10.008ms	335	350	95.71
		aes_ctr_fi	13.000s	132.892us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	43.000s	2.074ms	49	50	98.00
		aes_control_fi	52.000s	10.007ms	277	300	92.33
		aes_ctr_fi	13.000s	132.892us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	43.000s	2.074ms	49	50	98.00
		aes_control_fi	52.000s	10.007ms	277	300	92.33
		aes_cipher_fi	49.000s	10.008ms	335	350	95.71
V2S		TOTAL			945	985	95.94
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	3.800m	7.579ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1552	1602	96.88

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	13	100.00
V2S	11	11	7	63.64
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.34	98.54	96.30	99.42	95.71	97.64	97.78	99.11	97.01

Failure Buckets

Job aes_masked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 19 failures:
- Test aes_control_fi has 15 failures.
  - 6.aes_control_fi.39532951607926515307205722148823055880361156706929975731219300138955365011966
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/6.aes_control_fi/latest/run.log
```
  Job ID: smart:9c8abb6f-e67f-42ca-8a66-6fa1beeb9bd6
```
  - 18.aes_control_fi.81736174746698476144133095894510898312731607937685035425569158614776463440821
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/18.aes_control_fi/latest/run.log
```
  Job ID: smart:923197c6-58d6-445d-93a9-d1012944b1e4
```
  - ... and 13 more failures.
- Test aes_cipher_fi has 4 failures.
  - 6.aes_cipher_fi.109767370203660794483998800993790802567854734052152448097406363977671266168618
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/6.aes_cipher_fi/latest/run.log
```
  Job ID: smart:d94cf20d-32cd-45dc-b295-f8f4d196a70e
```
  - 102.aes_cipher_fi.103804044094115684532210675612751400447506701749240042277311522874805519421899
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/102.aes_cipher_fi/latest/run.log
```
  Job ID: smart:4d00ead9-18eb-4660-a4ea-49ab151508b2
```
  - ... and 2 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 11 failures:
- Test aes_cipher_fi has 11 failures.
  - 25.aes_cipher_fi.48830394684148884321453291593987349228133844127194706127626643160270857297017
    Line 321, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/25.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10021701796 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10021701796 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 26.aes_cipher_fi.83601796380526140183828695720360371014914988177009181799680832752836433110173
    Line 323, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/26.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10046375393 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10046375393 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 9 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 8 failures:
- Test aes_control_fi has 8 failures.
  - 40.aes_control_fi.105667159383032004410973989871458946711030343167209151536638932052239986514140
    Line 321, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/40.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10018846482 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10018846482 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 78.aes_control_fi.85334577563431184697587758293911967204043725301783172723996284344421399588636
    Line 328, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/78.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10036182359 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10036182359 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 6 failures:

Test aes_stress_all_with_rand_reset has 6 failures.

0.aes_stress_all_with_rand_reset.20119279123358732925275029671879441249166416737967219132582440604696217622938
Line 938, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2326932207 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 2326932207 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.79823966866619332284451413526596296457411357093031114475489745806404773341868
Line 1024, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 3872711493 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 3872711493 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 2 failures:

Test aes_stress_all_with_rand_reset has 2 failures.

2.aes_stress_all_with_rand_reset.50385021263839992556539591756357296273990787327998733577358491898405421036258
Line 886, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 397991678 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 397991678 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

7.aes_stress_all_with_rand_reset.96988764724628607029997288114384968466209304129895880593131624394118498379505
Line 1533, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/7.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 6106261944 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 6106261944 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_vseq.sv:837) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:
- Test aes_stress_all_with_rand_reset has 2 failures.
  - 5.aes_stress_all_with_rand_reset.82264155145227236395526884139060796713094517534154390678777136259012655362716
    Line 328, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/5.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 248684632 ps: (cip_base_vseq.sv:837) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 248684632 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 6.aes_stress_all_with_rand_reset.56041951970303082350367328067289825246500538414478805404765192329302825928057
    Line 983, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/6.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 7578879776 ps: (cip_base_vseq.sv:837) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 7578879776 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_fi_vseq.sv:69) virtual_sequencer [aes_fi_vseq] Was Able to finish without clearing reset has 1 failures:
- Test aes_fi has 1 failures.
  - 14.aes_fi.105964599854441330750170591665906113698461604166524843514019596091276154511611
    Line 239576, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/14.aes_fi/latest/run.log
```
  UVM_FATAL @ 2074256070 ps: (aes_fi_vseq.sv:69) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.aes_fi_vseq] Was Able to finish without clearing reset
  UVM_INFO @ 2074256070 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 44.aes_core_fi.6618876888073824264336172263942878804610698916278057352269415362886027419599
    Line 314, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/44.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10020975539 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10020975539 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```