AES/MASKED Simulation Results

Monday July 29 2024 23:02:32 UTC

GitHub Revision: `39f3866b56`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 91682663165753342493852681547271085771042321116470426223748766059309541455602

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	58.388us	1	1	100.00
V1	smoke	aes_smoke	20.000s	726.493us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	86.861us	5	5	100.00
V1	csr_rw	aes_csr_rw	3.000s	53.900us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	9.000s	188.216us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	4.000s	141.757us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	3.000s	71.891us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	3.000s	53.900us	20	20	100.00
		aes_csr_aliasing	4.000s	141.757us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	20.000s	726.493us	50	50	100.00
		aes_config_error	4.433m	7.168ms	50	50	100.00
		aes_stress	21.000s	79.845us	50	50	100.00
V2	key_length	aes_smoke	20.000s	726.493us	50	50	100.00
		aes_config_error	4.433m	7.168ms	50	50	100.00
		aes_stress	21.000s	79.845us	50	50	100.00
V2	back2back	aes_stress	21.000s	79.845us	50	50	100.00
		aes_b2b	28.000s	873.660us	50	50	100.00
V2	backpressure	aes_stress	21.000s	79.845us	50	50	100.00
V2	multi_message	aes_smoke	20.000s	726.493us	50	50	100.00
		aes_config_error	4.433m	7.168ms	50	50	100.00
		aes_stress	21.000s	79.845us	50	50	100.00
		aes_alert_reset	26.000s	1.207ms	50	50	100.00
V2	failure_test	aes_man_cfg_err	14.000s	58.818us	50	50	100.00
		aes_config_error	4.433m	7.168ms	50	50	100.00
		aes_alert_reset	26.000s	1.207ms	50	50	100.00
V2	trigger_clear_test	aes_clear	1.667m	3.030ms	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	11.000s	594.744us	1	1	100.00
V2	reset_recovery	aes_alert_reset	26.000s	1.207ms	50	50	100.00
V2	stress	aes_stress	21.000s	79.845us	50	50	100.00
V2	sideload	aes_stress	21.000s	79.845us	50	50	100.00
		aes_sideload	15.000s	1.745ms	50	50	100.00
V2	deinitialization	aes_deinit	16.000s	376.071us	50	50	100.00
V2	stress_all	aes_stress_all	1.850m	1.432ms	10	10	100.00
V2	alert_test	aes_alert_test	8.000s	219.083us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	6.000s	144.431us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	6.000s	144.431us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	86.861us	5	5	100.00
		aes_csr_rw	3.000s	53.900us	20	20	100.00
		aes_csr_aliasing	4.000s	141.757us	5	5	100.00
		aes_same_csr_outstanding	4.000s	216.689us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	86.861us	5	5	100.00
		aes_csr_rw	3.000s	53.900us	20	20	100.00
		aes_csr_aliasing	4.000s	141.757us	5	5	100.00
		aes_same_csr_outstanding	4.000s	216.689us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	36.000s	5.162ms	50	50	100.00
V2S	fault_inject	aes_fi	55.000s	8.396ms	50	50	100.00
		aes_control_fi	45.000s	10.015ms	280	300	93.33
		aes_cipher_fi	49.000s	10.006ms	338	350	96.57
V2S	shadow_reg_update_error	aes_shadow_reg_errors	3.000s	91.163us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	3.000s	91.163us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	3.000s	91.163us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	3.000s	91.163us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	4.000s	398.380us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	15.000s	1.274ms	5	5	100.00
		aes_tl_intg_err	5.000s	1.867ms	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	5.000s	1.867ms	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	26.000s	1.207ms	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	3.000s	91.163us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	20.000s	726.493us	50	50	100.00
		aes_stress	21.000s	79.845us	50	50	100.00
		aes_alert_reset	26.000s	1.207ms	50	50	100.00
		aes_core_fi	1.850m	10.037ms	69	70	98.57
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	3.000s	91.163us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	13.000s	66.913us	50	50	100.00
		aes_stress	21.000s	79.845us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	21.000s	79.845us	50	50	100.00
		aes_sideload	15.000s	1.745ms	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	13.000s	66.913us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	13.000s	66.913us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	13.000s	66.913us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	13.000s	66.913us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	13.000s	66.913us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	21.000s	79.845us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	21.000s	79.845us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	55.000s	8.396ms	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	55.000s	8.396ms	50	50	100.00
		aes_control_fi	45.000s	10.015ms	280	300	93.33
		aes_cipher_fi	49.000s	10.006ms	338	350	96.57
		aes_ctr_fi	14.000s	86.040us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	55.000s	8.396ms	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	55.000s	8.396ms	50	50	100.00
		aes_control_fi	45.000s	10.015ms	280	300	93.33
		aes_cipher_fi	49.000s	10.006ms	338	350	96.57
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	49.000s	10.006ms	338	350	96.57
V2S	sec_cm_ctr_fsm_sparse	aes_fi	55.000s	8.396ms	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	55.000s	8.396ms	50	50	100.00
		aes_control_fi	45.000s	10.015ms	280	300	93.33
		aes_ctr_fi	14.000s	86.040us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	55.000s	8.396ms	50	50	100.00
		aes_control_fi	45.000s	10.015ms	280	300	93.33
		aes_cipher_fi	49.000s	10.006ms	338	350	96.57
		aes_ctr_fi	14.000s	86.040us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	26.000s	1.207ms	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	55.000s	8.396ms	50	50	100.00
		aes_control_fi	45.000s	10.015ms	280	300	93.33
		aes_cipher_fi	49.000s	10.006ms	338	350	96.57
		aes_ctr_fi	14.000s	86.040us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	55.000s	8.396ms	50	50	100.00
		aes_control_fi	45.000s	10.015ms	280	300	93.33
		aes_cipher_fi	49.000s	10.006ms	338	350	96.57
		aes_ctr_fi	14.000s	86.040us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	55.000s	8.396ms	50	50	100.00
		aes_control_fi	45.000s	10.015ms	280	300	93.33
		aes_ctr_fi	14.000s	86.040us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	55.000s	8.396ms	50	50	100.00
		aes_control_fi	45.000s	10.015ms	280	300	93.33
		aes_cipher_fi	49.000s	10.006ms	338	350	96.57
V2S		TOTAL			952	985	96.65
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	5.217m	20.693ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1559	1602	97.32

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	13	100.00
V2S	11	11	8	72.73
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.36	98.55	96.32	99.43	95.85	97.72	97.78	98.96	96.81

Failure Buckets

Job aes_masked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 22 failures:
- Test aes_cipher_fi has 5 failures.
  - 12.aes_cipher_fi.104656405696823527036604548630044884854065509513076198168206355849452945153157
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/12.aes_cipher_fi/latest/run.log
```
  Job ID: smart:80b18704-0f66-47f4-892f-bed4febecf47
```
  - 63.aes_cipher_fi.77184272378948044928798149196632952696644185122830307661819779396305128201718
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/63.aes_cipher_fi/latest/run.log
```
  Job ID: smart:51f21fb6-763d-46cc-84ec-fb3a57d5dbab
```
  - ... and 3 more failures.
- Test aes_control_fi has 17 failures.
  - 22.aes_control_fi.80979345815002235220266418317351121833207926446734695338464543967998740345650
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/22.aes_control_fi/latest/run.log
```
  Job ID: smart:5d628505-ea6f-4dde-94b3-7f787d662dd2
```
  - 34.aes_control_fi.18754484209476218095063148572217604954419992608286194822598708360125977907147
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/34.aes_control_fi/latest/run.log
```
  Job ID: smart:af9f630e-a4b4-48b4-8723-0789191bfd4f
```
  - ... and 15 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 7 failures:
- Test aes_cipher_fi has 7 failures.
  - 19.aes_cipher_fi.41185263045323374664382173669033346041702603688160577361100177996920374966926
    Line 326, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/19.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10006492072 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006492072 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 85.aes_cipher_fi.55282316228581476264694112862926983978729054376791676530109118823444407224814
    Line 312, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/85.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10026812394 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10026812394 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues

has 6 failures:

Test aes_stress_all_with_rand_reset has 6 failures.

0.aes_stress_all_with_rand_reset.60286527308431121343196460361343214192478463114724407496533967797425574401735
Line 413, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 641142247 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 641142247 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.115103595048014120066825667339041578783703215162856062911820400561326789336335
Line 674, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 808998569 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 808998569 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues

has 4 failures:

Test aes_stress_all_with_rand_reset has 4 failures.

2.aes_stress_all_with_rand_reset.76747869194929231913165190973617880992822644486605817367501836020852939331985
Line 1079, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1608726384 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1608726384 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.aes_stress_all_with_rand_reset.102376597542130985195367657870663573906194310977981551785632020149758229886107
Line 704, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/5.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 269239393 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 269239393 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 3 failures:
- Test aes_control_fi has 3 failures.
  - 12.aes_control_fi.68636185487944855880606701065469625077113240169663727851681170659804992594016
    Line 317, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/12.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10013826472 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10013826472 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 105.aes_control_fi.63636366902448024905230049979241689446697250810568874788893685404648922340517
    Line 320, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/105.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10014084180 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10014084180 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=8) has 1 failures:
- Test aes_core_fi has 1 failures.
  - 69.aes_core_fi.53051418617371087664959878162333250292279588276745676013257423022186601525524
    Line 314, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/69.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10036794835 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0xb8a86084, Comparison=CompareOpEq, exp_data=0x0, call_count=8)
  UVM_INFO @ 10036794835 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```