AES/MASKED Simulation Results

Wednesday July 31 2024 23:02:38 UTC

GitHub Revision: `e9b7e615a7`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 25204348267605859133056659113100703417171299070132656462514712657132693373848

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	5.000s	83.177us	1	1	100.00
V1	smoke	aes_smoke	12.000s	703.706us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	5.000s	77.309us	5	5	100.00
V1	csr_rw	aes_csr_rw	3.000s	49.869us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	11.000s	3.066ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	472.936us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	3.000s	63.879us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	3.000s	49.869us	20	20	100.00
		aes_csr_aliasing	5.000s	472.936us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	12.000s	703.706us	50	50	100.00
		aes_config_error	14.000s	73.024us	50	50	100.00
		aes_stress	16.000s	437.099us	50	50	100.00
V2	key_length	aes_smoke	12.000s	703.706us	50	50	100.00
		aes_config_error	14.000s	73.024us	50	50	100.00
		aes_stress	16.000s	437.099us	50	50	100.00
V2	back2back	aes_stress	16.000s	437.099us	50	50	100.00
		aes_b2b	39.000s	780.368us	50	50	100.00
V2	backpressure	aes_stress	16.000s	437.099us	50	50	100.00
V2	multi_message	aes_smoke	12.000s	703.706us	50	50	100.00
		aes_config_error	14.000s	73.024us	50	50	100.00
		aes_stress	16.000s	437.099us	50	50	100.00
		aes_alert_reset	17.000s	1.371ms	50	50	100.00
V2	failure_test	aes_man_cfg_err	14.000s	68.970us	50	50	100.00
		aes_config_error	14.000s	73.024us	50	50	100.00
		aes_alert_reset	17.000s	1.371ms	50	50	100.00
V2	trigger_clear_test	aes_clear	1.483m	2.921ms	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	1.050m	3.514ms	1	1	100.00
V2	reset_recovery	aes_alert_reset	17.000s	1.371ms	50	50	100.00
V2	stress	aes_stress	16.000s	437.099us	50	50	100.00
V2	sideload	aes_stress	16.000s	437.099us	50	50	100.00
		aes_sideload	15.000s	630.686us	50	50	100.00
V2	deinitialization	aes_deinit	17.000s	1.264ms	50	50	100.00
V2	stress_all	aes_stress_all	1.517m	1.425ms	10	10	100.00
V2	alert_test	aes_alert_test	9.000s	67.516us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	8.000s	101.817us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	8.000s	101.817us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	5.000s	77.309us	5	5	100.00
		aes_csr_rw	3.000s	49.869us	20	20	100.00
		aes_csr_aliasing	5.000s	472.936us	5	5	100.00
		aes_same_csr_outstanding	7.000s	117.613us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	5.000s	77.309us	5	5	100.00
		aes_csr_rw	3.000s	49.869us	20	20	100.00
		aes_csr_aliasing	5.000s	472.936us	5	5	100.00
		aes_same_csr_outstanding	7.000s	117.613us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	1.883m	3.442ms	50	50	100.00
V2S	fault_inject	aes_fi	2.283m	6.769ms	50	50	100.00
		aes_control_fi	45.000s	10.015ms	290	300	96.67
		aes_cipher_fi	48.000s	10.005ms	335	350	95.71
V2S	shadow_reg_update_error	aes_shadow_reg_errors	7.000s	66.379us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	7.000s	66.379us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	7.000s	66.379us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	7.000s	66.379us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	4.000s	104.554us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	16.000s	1.575ms	5	5	100.00
		aes_tl_intg_err	8.000s	184.415us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	8.000s	184.415us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	17.000s	1.371ms	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	7.000s	66.379us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	12.000s	703.706us	50	50	100.00
		aes_stress	16.000s	437.099us	50	50	100.00
		aes_alert_reset	17.000s	1.371ms	50	50	100.00
		aes_core_fi	28.000s	793.108us	66	70	94.29
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	7.000s	66.379us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	9.000s	58.798us	50	50	100.00
		aes_stress	16.000s	437.099us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	16.000s	437.099us	50	50	100.00
		aes_sideload	15.000s	630.686us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	9.000s	58.798us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	9.000s	58.798us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	9.000s	58.798us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	9.000s	58.798us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	9.000s	58.798us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	16.000s	437.099us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	16.000s	437.099us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	2.283m	6.769ms	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	2.283m	6.769ms	50	50	100.00
		aes_control_fi	45.000s	10.015ms	290	300	96.67
		aes_cipher_fi	48.000s	10.005ms	335	350	95.71
		aes_ctr_fi	10.000s	170.649us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	2.283m	6.769ms	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	2.283m	6.769ms	50	50	100.00
		aes_control_fi	45.000s	10.015ms	290	300	96.67
		aes_cipher_fi	48.000s	10.005ms	335	350	95.71
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	48.000s	10.005ms	335	350	95.71
V2S	sec_cm_ctr_fsm_sparse	aes_fi	2.283m	6.769ms	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	2.283m	6.769ms	50	50	100.00
		aes_control_fi	45.000s	10.015ms	290	300	96.67
		aes_ctr_fi	10.000s	170.649us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	2.283m	6.769ms	50	50	100.00
		aes_control_fi	45.000s	10.015ms	290	300	96.67
		aes_cipher_fi	48.000s	10.005ms	335	350	95.71
		aes_ctr_fi	10.000s	170.649us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	17.000s	1.371ms	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	2.283m	6.769ms	50	50	100.00
		aes_control_fi	45.000s	10.015ms	290	300	96.67
		aes_cipher_fi	48.000s	10.005ms	335	350	95.71
		aes_ctr_fi	10.000s	170.649us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	2.283m	6.769ms	50	50	100.00
		aes_control_fi	45.000s	10.015ms	290	300	96.67
		aes_cipher_fi	48.000s	10.005ms	335	350	95.71
		aes_ctr_fi	10.000s	170.649us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	2.283m	6.769ms	50	50	100.00
		aes_control_fi	45.000s	10.015ms	290	300	96.67
		aes_ctr_fi	10.000s	170.649us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	2.283m	6.769ms	50	50	100.00
		aes_control_fi	45.000s	10.015ms	290	300	96.67
		aes_cipher_fi	48.000s	10.005ms	335	350	95.71
V2S		TOTAL			956	985	97.06
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	4.167m	10.488ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1563	1602	97.57

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	13	100.00
V2S	11	11	8	72.73
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.32	98.53	96.25	99.42	95.65	97.64	97.78	98.96	96.81

Failure Buckets

Job aes_masked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 14 failures:
- Test aes_control_fi has 8 failures.
  - 15.aes_control_fi.99552091946251051845751910202046146024935310496416840366317535959986736822999
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/15.aes_control_fi/latest/run.log
```
  Job ID: smart:b1847bf8-6647-481e-bbf9-6cd1e98d62af
```
  - 44.aes_control_fi.50604497178072251172274101912232301105191689700618129629215405522871511607714
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/44.aes_control_fi/latest/run.log
```
  Job ID: smart:04d143b1-6345-4ac4-888a-63e3301b431a
```
  - ... and 6 more failures.
- Test aes_cipher_fi has 6 failures.
  - 29.aes_cipher_fi.30783239425812953070307924111223523000360091324912404223005966941246295605622
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/29.aes_cipher_fi/latest/run.log
```
  Job ID: smart:a3fd72d8-1afe-4337-add3-7c2c427fd02f
```
  - 75.aes_cipher_fi.114954663413908386200535271332185967250237487878275392342212548192399054610240
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/75.aes_cipher_fi/latest/run.log
```
  Job ID: smart:4191941c-d2c5-433f-8c24-1db9ac45cce1
```
  - ... and 4 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 9 failures:
- Test aes_cipher_fi has 9 failures.
  - 15.aes_cipher_fi.35682956108386103774434441988239471621387466224670097840896521356710521249523
    Line 320, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/15.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10084362749 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10084362749 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 21.aes_cipher_fi.11225673079548728313948795722686482309653835235036289018903272349566882188636
    Line 314, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/21.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10015697545 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10015697545 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 7 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 8 failures:

Test aes_stress_all_with_rand_reset has 8 failures.

0.aes_stress_all_with_rand_reset.111870317488089061472551558002229201997790337708694481289804712582769052705795
Line 933, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2146891642 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 2146891642 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.67631628557754529941141358277049853686060095407552424025131845969823543580804
Line 1409, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2922276260 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 2922276260 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 3 failures:
- Test aes_core_fi has 3 failures.
  - 16.aes_core_fi.71558696978364631741282248664382615179044404817042504275702318500626813528454
    Line 324, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/16.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10012246728 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10012246728 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 18.aes_core_fi.44341202533473439087709532219512656494802493564601399118326050658396790214632
    Line 321, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/18.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10016750651 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10016750651 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 2 failures:

Test aes_stress_all_with_rand_reset has 2 failures.

3.aes_stress_all_with_rand_reset.33876586033858001679326880886906320028794994601206955382923850346745311605968
Line 1044, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2203436591 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 2203436591 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.aes_stress_all_with_rand_reset.66995902289161314031401526052654687333352694578292047130506192010470187666274
Line 1439, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/5.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1427055693 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1427055693 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_control_fi has 2 failures.
  - 55.aes_control_fi.94624565404053792527709425493272331628751226271229778548647544007540337839176
    Line 315, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/55.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10020322765 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10020322765 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 60.aes_control_fi.62200056836501706493063125223912071453880530388834515479176370918865119726222
    Line 327, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/60.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10014791519 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10014791519 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_*/rtl/aes_cipher_core.sv,858): Assertion AesSecCmKeyMaskingInitialPrngUpdateSubBytes has failed (* cycles, starting * PS) has 1 failures:

Test aes_core_fi has 1 failures.

20.aes_core_fi.67806913929099295361196993896744495389798039676428791119004038280671352368494
Line 318, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/20.aes_core_fi/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_cipher_core.sv,858): (time 10928121 PS) Assertion tb.dut.u_aes_core.u_aes_cipher_core.gen_sec_cm_key_masking_svas.AesSecCmKeyMaskingInitialPrngUpdateSubBytes has failed (2 cycles, starting 10915775 PS)
            (SecAllowForcingMasks && force_masks_i) || dec_key_gen_o == SP2V_HIGH)
                                                                                 |
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_cipher_core.sv,865): (time 10928121 PS) Assertion tb.dut.u_aes_core.u_aes_cipher_core.gen_sec_cm_key_masking_svas.AesSecCmKeyMaskingInitialPrngUpdateKeyExpand has failed (2 cycles, starting 10915775 PS)
  UVM_ERROR @  10928121 ps: (aes_cipher_core.sv:858) [ASSERT FAILED] AesSecCmKeyMaskingInitialPrngUpdateSubBytes