AES/MASKED Simulation Results

Tuesday July 30 2024 23:02:08 UTC

GitHub Revision: `fdfa12db04`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 101467584611478134588291649782725219255540557286164709436567235390830780957271

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	4.000s	79.878us	1	1	100.00
V1	smoke	aes_smoke	12.000s	858.456us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	4.000s	113.495us	5	5	100.00
V1	csr_rw	aes_csr_rw	4.000s	74.283us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	10.000s	587.329us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	4.000s	262.719us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	13.000s	79.778us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	4.000s	74.283us	20	20	100.00
		aes_csr_aliasing	4.000s	262.719us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	12.000s	858.456us	50	50	100.00
		aes_config_error	14.000s	872.809us	50	50	100.00
		aes_stress	42.000s	1.223ms	50	50	100.00
V2	key_length	aes_smoke	12.000s	858.456us	50	50	100.00
		aes_config_error	14.000s	872.809us	50	50	100.00
		aes_stress	42.000s	1.223ms	50	50	100.00
V2	back2back	aes_stress	42.000s	1.223ms	50	50	100.00
		aes_b2b	40.000s	438.742us	50	50	100.00
V2	backpressure	aes_stress	42.000s	1.223ms	50	50	100.00
V2	multi_message	aes_smoke	12.000s	858.456us	50	50	100.00
		aes_config_error	14.000s	872.809us	50	50	100.00
		aes_stress	42.000s	1.223ms	50	50	100.00
		aes_alert_reset	1.533m	11.773ms	49	50	98.00
V2	failure_test	aes_man_cfg_err	9.000s	66.926us	50	50	100.00
		aes_config_error	14.000s	872.809us	50	50	100.00
		aes_alert_reset	1.533m	11.773ms	49	50	98.00
V2	trigger_clear_test	aes_clear	38.000s	991.934us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	11.000s	1.470ms	1	1	100.00
V2	reset_recovery	aes_alert_reset	1.533m	11.773ms	49	50	98.00
V2	stress	aes_stress	42.000s	1.223ms	50	50	100.00
V2	sideload	aes_stress	42.000s	1.223ms	50	50	100.00
		aes_sideload	42.000s	1.429ms	50	50	100.00
V2	deinitialization	aes_deinit	11.000s	1.062ms	50	50	100.00
V2	stress_all	aes_stress_all	1.833m	7.280ms	10	10	100.00
V2	alert_test	aes_alert_test	7.000s	81.517us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	13.000s	134.484us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	13.000s	134.484us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	4.000s	113.495us	5	5	100.00
		aes_csr_rw	4.000s	74.283us	20	20	100.00
		aes_csr_aliasing	4.000s	262.719us	5	5	100.00
		aes_same_csr_outstanding	14.000s	66.133us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	4.000s	113.495us	5	5	100.00
		aes_csr_rw	4.000s	74.283us	20	20	100.00
		aes_csr_aliasing	4.000s	262.719us	5	5	100.00
		aes_same_csr_outstanding	14.000s	66.133us	20	20	100.00
V2		TOTAL			500	501	99.80
V2S	reseeding	aes_reseed	15.000s	1.394ms	50	50	100.00
V2S	fault_inject	aes_fi	13.000s	844.273us	50	50	100.00
		aes_control_fi	49.000s	10.009ms	280	300	93.33
		aes_cipher_fi	50.000s	10.007ms	336	350	96.00
V2S	shadow_reg_update_error	aes_shadow_reg_errors	7.000s	86.866us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	7.000s	86.866us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	7.000s	86.866us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	7.000s	86.866us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	8.000s	160.795us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	8.000s	1.461ms	5	5	100.00
		aes_tl_intg_err	9.000s	210.251us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	9.000s	210.251us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	1.533m	11.773ms	49	50	98.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	7.000s	86.866us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	12.000s	858.456us	50	50	100.00
		aes_stress	42.000s	1.223ms	50	50	100.00
		aes_alert_reset	1.533m	11.773ms	49	50	98.00
		aes_core_fi	52.000s	10.027ms	67	70	95.71
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	7.000s	86.866us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	5.000s	69.542us	50	50	100.00
		aes_stress	42.000s	1.223ms	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	42.000s	1.223ms	50	50	100.00
		aes_sideload	42.000s	1.429ms	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	5.000s	69.542us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	5.000s	69.542us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	5.000s	69.542us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	5.000s	69.542us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	5.000s	69.542us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	42.000s	1.223ms	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	42.000s	1.223ms	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	13.000s	844.273us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	13.000s	844.273us	50	50	100.00
		aes_control_fi	49.000s	10.009ms	280	300	93.33
		aes_cipher_fi	50.000s	10.007ms	336	350	96.00
		aes_ctr_fi	14.000s	667.673us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	13.000s	844.273us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	13.000s	844.273us	50	50	100.00
		aes_control_fi	49.000s	10.009ms	280	300	93.33
		aes_cipher_fi	50.000s	10.007ms	336	350	96.00
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	50.000s	10.007ms	336	350	96.00
V2S	sec_cm_ctr_fsm_sparse	aes_fi	13.000s	844.273us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	13.000s	844.273us	50	50	100.00
		aes_control_fi	49.000s	10.009ms	280	300	93.33
		aes_ctr_fi	14.000s	667.673us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	13.000s	844.273us	50	50	100.00
		aes_control_fi	49.000s	10.009ms	280	300	93.33
		aes_cipher_fi	50.000s	10.007ms	336	350	96.00
		aes_ctr_fi	14.000s	667.673us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	1.533m	11.773ms	49	50	98.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	13.000s	844.273us	50	50	100.00
		aes_control_fi	49.000s	10.009ms	280	300	93.33
		aes_cipher_fi	50.000s	10.007ms	336	350	96.00
		aes_ctr_fi	14.000s	667.673us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	13.000s	844.273us	50	50	100.00
		aes_control_fi	49.000s	10.009ms	280	300	93.33
		aes_cipher_fi	50.000s	10.007ms	336	350	96.00
		aes_ctr_fi	14.000s	667.673us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	13.000s	844.273us	50	50	100.00
		aes_control_fi	49.000s	10.009ms	280	300	93.33
		aes_ctr_fi	14.000s	667.673us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	13.000s	844.273us	50	50	100.00
		aes_control_fi	49.000s	10.009ms	280	300	93.33
		aes_cipher_fi	50.000s	10.007ms	336	350	96.00
V2S		TOTAL			948	985	96.24
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	5.733m	9.216ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1554	1602	97.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	12	92.31
V2S	11	11	8	72.73
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.35	98.54	96.28	99.41	95.83	97.72	100.00	98.96	97.21

Failure Buckets

Job aes_masked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 18 failures:
- Test aes_control_fi has 12 failures.
  - 17.aes_control_fi.73821705762708357456217107544909466526615429162774544637179821279735346658632
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/17.aes_control_fi/latest/run.log
```
  Job ID: smart:719f874a-cdde-4cc0-913d-3ddf3fb927d4
```
  - 35.aes_control_fi.100321569972238242381462986856053142431416591142822608925581791656391752589601
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/35.aes_control_fi/latest/run.log
```
  Job ID: smart:3324b950-d938-47ae-8f78-86f2c59396af
```
  - ... and 10 more failures.
- Test aes_cipher_fi has 6 failures.
  - 129.aes_cipher_fi.100366695215760191754328799878245096153909352983622120805819709328588658316215
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/129.aes_cipher_fi/latest/run.log
```
  Job ID: smart:dcf05e23-9df6-4dc6-935d-d7b2f8442c53
```
  - 218.aes_cipher_fi.53561851431921376721051221476974359768837114185050184095049601149085176945287
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/218.aes_cipher_fi/latest/run.log
```
  Job ID: smart:6bbf0fbc-6cb7-4ba0-834c-3bb622ff69f1
```
  - ... and 4 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 8 failures:
- Test aes_cipher_fi has 8 failures.
  - 3.aes_cipher_fi.75603066627288030705860507379534147892339901560245869562769016637355417279722
    Line 315, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/3.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10006610911 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006610911 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 49.aes_cipher_fi.83144141583088292098094203441680112072733410837895877650038315301371209742987
    Line 321, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/49.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10018038941 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10018038941 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 8 failures:
- Test aes_control_fi has 8 failures.
  - 8.aes_control_fi.110299920271104942774791303676882612092301651777146759497197790430435717573476
    Line 315, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/8.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10012201087 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10012201087 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 49.aes_control_fi.5960699676535516716417794453343191323264273102952205854738818281331492427036
    Line 323, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/49.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10007644678 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10007644678 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 7 failures:

Test aes_stress_all_with_rand_reset has 7 failures.

1.aes_stress_all_with_rand_reset.70242112116137599819626326169120365804534920903233730147163771412931309505471
Line 1404, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1675629038 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1675629038 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.aes_stress_all_with_rand_reset.90709798619581225577494003507491220287324761015889148123465205763422767703841
Line 878, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1603193687 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1603193687 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 3 failures:

Test aes_stress_all_with_rand_reset has 3 failures.

0.aes_stress_all_with_rand_reset.29991211369010714705263270496799237909080777577881565229899455827568944288499
Line 951, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 6805786815 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 6805786815 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.aes_stress_all_with_rand_reset.15806991008618966943279949980965532112186170874730123565043815931248679223251
Line 977, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 6694267513 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 6694267513 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_core_fi has 2 failures.
  - 34.aes_core_fi.41360413118749440769974084003273324274930696427491305584296398119978557348752
    Line 315, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/34.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10026695293 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10026695293 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 45.aes_core_fi.13340154723251148695223985722236153888482021817308279581910630611268291086510
    Line 323, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/45.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10032948498 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10032948498 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,987): Assertion AesSecCmDataRegLocalEscDataOut has failed (* cycles, starting * PS) has 1 failures:
- Test aes_alert_reset has 1 failures.
  - 10.aes_alert_reset.24542831976672350973472377253061772079240448432293393517759646865254611037685
    Line 2445, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/10.aes_alert_reset/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,987): (time 7975626 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 7965525 PS)
  UVM_ERROR @   7975626 ps: (aes_core.sv:987) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut
  UVM_INFO @   7975626 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=8) has 1 failures:
- Test aes_core_fi has 1 failures.
  - 65.aes_core_fi.86218908361066849160685112328273169070849658135674447988778089487739363754397
    Line 310, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/65.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10186500396 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0xb81c9a84, Comparison=CompareOpEq, exp_data=0x0, call_count=8)
  UVM_INFO @ 10186500396 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```