AES/MASKED Simulation Results

Friday August 02 2024 23:02:48 UTC

GitHub Revision: `c8985d6745`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 75989420798843487383163268541581889763599806834398027919895759109584083292465

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	95.634us	1	1	100.00
V1	smoke	aes_smoke	26.000s	3.530ms	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	4.000s	66.407us	5	5	100.00
V1	csr_rw	aes_csr_rw	13.000s	67.662us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	11.000s	339.416us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	308.939us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	8.000s	65.439us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	13.000s	67.662us	20	20	100.00
		aes_csr_aliasing	5.000s	308.939us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	26.000s	3.530ms	50	50	100.00
		aes_config_error	35.000s	2.406ms	50	50	100.00
		aes_stress	1.083m	2.121ms	50	50	100.00
V2	key_length	aes_smoke	26.000s	3.530ms	50	50	100.00
		aes_config_error	35.000s	2.406ms	50	50	100.00
		aes_stress	1.083m	2.121ms	50	50	100.00
V2	back2back	aes_stress	1.083m	2.121ms	50	50	100.00
		aes_b2b	56.000s	655.672us	50	50	100.00
V2	backpressure	aes_stress	1.083m	2.121ms	50	50	100.00
V2	multi_message	aes_smoke	26.000s	3.530ms	50	50	100.00
		aes_config_error	35.000s	2.406ms	50	50	100.00
		aes_stress	1.083m	2.121ms	50	50	100.00
		aes_alert_reset	18.000s	2.093ms	50	50	100.00
V2	failure_test	aes_man_cfg_err	9.000s	93.977us	50	50	100.00
		aes_config_error	35.000s	2.406ms	50	50	100.00
		aes_alert_reset	18.000s	2.093ms	50	50	100.00
V2	trigger_clear_test	aes_clear	1.183m	2.079ms	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	14.000s	1.633ms	1	1	100.00
V2	reset_recovery	aes_alert_reset	18.000s	2.093ms	50	50	100.00
V2	stress	aes_stress	1.083m	2.121ms	50	50	100.00
V2	sideload	aes_stress	1.083m	2.121ms	50	50	100.00
		aes_sideload	8.000s	86.587us	50	50	100.00
V2	deinitialization	aes_deinit	35.000s	1.001ms	50	50	100.00
V2	stress_all	aes_stress_all	3.417m	7.270ms	10	10	100.00
V2	alert_test	aes_alert_test	9.000s	50.688us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	7.000s	961.128us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	7.000s	961.128us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	4.000s	66.407us	5	5	100.00
		aes_csr_rw	13.000s	67.662us	20	20	100.00
		aes_csr_aliasing	5.000s	308.939us	5	5	100.00
		aes_same_csr_outstanding	8.000s	89.142us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	4.000s	66.407us	5	5	100.00
		aes_csr_rw	13.000s	67.662us	20	20	100.00
		aes_csr_aliasing	5.000s	308.939us	5	5	100.00
		aes_same_csr_outstanding	8.000s	89.142us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	35.000s	3.814ms	50	50	100.00
V2S	fault_inject	aes_fi	35.000s	3.736ms	49	50	98.00
		aes_control_fi	49.000s	10.011ms	275	300	91.67
		aes_cipher_fi	30.000s	10.022ms	339	350	96.86
V2S	shadow_reg_update_error	aes_shadow_reg_errors	8.000s	288.048us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	8.000s	288.048us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	8.000s	288.048us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	8.000s	288.048us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	9.000s	145.036us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	16.000s	1.340ms	5	5	100.00
		aes_tl_intg_err	8.000s	104.072us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	8.000s	104.072us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	18.000s	2.093ms	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	8.000s	288.048us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	26.000s	3.530ms	50	50	100.00
		aes_stress	1.083m	2.121ms	50	50	100.00
		aes_alert_reset	18.000s	2.093ms	50	50	100.00
		aes_core_fi	1.383m	10.011ms	67	70	95.71
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	8.000s	288.048us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	8.000s	208.909us	50	50	100.00
		aes_stress	1.083m	2.121ms	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	1.083m	2.121ms	50	50	100.00
		aes_sideload	8.000s	86.587us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	8.000s	208.909us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	8.000s	208.909us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	8.000s	208.909us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	8.000s	208.909us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	8.000s	208.909us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	1.083m	2.121ms	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	1.083m	2.121ms	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	35.000s	3.736ms	49	50	98.00
V2S	sec_cm_main_fsm_redun	aes_fi	35.000s	3.736ms	49	50	98.00
		aes_control_fi	49.000s	10.011ms	275	300	91.67
		aes_cipher_fi	30.000s	10.022ms	339	350	96.86
		aes_ctr_fi	8.000s	61.355us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	35.000s	3.736ms	49	50	98.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	35.000s	3.736ms	49	50	98.00
		aes_control_fi	49.000s	10.011ms	275	300	91.67
		aes_cipher_fi	30.000s	10.022ms	339	350	96.86
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	30.000s	10.022ms	339	350	96.86
V2S	sec_cm_ctr_fsm_sparse	aes_fi	35.000s	3.736ms	49	50	98.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	35.000s	3.736ms	49	50	98.00
		aes_control_fi	49.000s	10.011ms	275	300	91.67
		aes_ctr_fi	8.000s	61.355us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	35.000s	3.736ms	49	50	98.00
		aes_control_fi	49.000s	10.011ms	275	300	91.67
		aes_cipher_fi	30.000s	10.022ms	339	350	96.86
		aes_ctr_fi	8.000s	61.355us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	18.000s	2.093ms	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	35.000s	3.736ms	49	50	98.00
		aes_control_fi	49.000s	10.011ms	275	300	91.67
		aes_cipher_fi	30.000s	10.022ms	339	350	96.86
		aes_ctr_fi	8.000s	61.355us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	35.000s	3.736ms	49	50	98.00
		aes_control_fi	49.000s	10.011ms	275	300	91.67
		aes_cipher_fi	30.000s	10.022ms	339	350	96.86
		aes_ctr_fi	8.000s	61.355us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	35.000s	3.736ms	49	50	98.00
		aes_control_fi	49.000s	10.011ms	275	300	91.67
		aes_ctr_fi	8.000s	61.355us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	35.000s	3.736ms	49	50	98.00
		aes_control_fi	49.000s	10.011ms	275	300	91.67
		aes_cipher_fi	30.000s	10.022ms	339	350	96.86
V2S		TOTAL			945	985	95.94
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	10.933m	156.676ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1552	1602	96.88

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	13	100.00
V2S	11	11	7	63.64
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.38	98.56	96.34	99.45	95.83	97.64	100.00	98.96	96.81

Failure Buckets

Job aes_masked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 23 failures:
- Test aes_control_fi has 16 failures.
  - 8.aes_control_fi.19023379977097250384547977491827765600004049629356732506206879830152916003842
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/8.aes_control_fi/latest/run.log
```
  Job ID: smart:8547f69e-97f4-4d81-8518-fe03dd28b4c7
```
  - 52.aes_control_fi.64078431374393576594396893062161409237941439100034296222926074975690283147542
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/52.aes_control_fi/latest/run.log
```
  Job ID: smart:ef066570-d575-410a-bb53-45a746658b93
```
  - ... and 14 more failures.
- Test aes_cipher_fi has 7 failures.
  - 73.aes_cipher_fi.67601235282874753208637069894488399832803661432488727273583820138666190059126
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/73.aes_cipher_fi/latest/run.log
```
  Job ID: smart:126c2099-10fd-424f-9383-5c23c69c13b0
```
  - 159.aes_cipher_fi.7548241663460911337022338228640883820881256870506885711395108355068601098158
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/159.aes_cipher_fi/latest/run.log
```
  Job ID: smart:6e7788f3-41f6-48dc-ba29-5f6dc3439b37
```
  - ... and 5 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 9 failures:

Test aes_stress_all_with_rand_reset has 9 failures.

0.aes_stress_all_with_rand_reset.97098888750821578409335019149958709871606231645867018746362795425475613117763
Line 1222, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 4505955876 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 4505955876 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.50619300842503075249225015400773840583273922413148508757072377670903285206003
Line 800, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 8801744824 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 8801744824 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 7 more failures.

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 9 failures:
- Test aes_control_fi has 9 failures.
  - 38.aes_control_fi.95503480919617750127187051085116068204734809347313941543343134473884034785862
    Line 314, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/38.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10068332900 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10068332900 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 59.aes_control_fi.93603144734200040843086128135100126042065626692993088607900466993301445029400
    Line 325, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/59.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10011449002 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10011449002 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 7 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 4 failures:
- Test aes_cipher_fi has 4 failures.
  - 19.aes_cipher_fi.17876489118328113835145258906819861435351568658089788196988336678831392539609
    Line 322, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/19.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10029811264 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10029811264 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 105.aes_cipher_fi.41715901341318709471903823773422462276887077206053487636592206592938962538497
    Line 321, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/105.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10028201431 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10028201431 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 3 failures:
- Test aes_core_fi has 3 failures.
  - 6.aes_core_fi.103435858656365725060225383533299118966355936029819660454583584681874440595809
    Line 310, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/6.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10004171462 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10004171462 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 14.aes_core_fi.21045290017564627807976522989712268687053836096690226618986256558323517777927
    Line 318, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/14.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10009643371 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10009643371 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 3.aes_stress_all_with_rand_reset.71293528236753392101073239164987850745940774575494314470526430058574974509577
    Line 1023, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 711249257 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 711249257 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_fi_vseq.sv:69) virtual_sequencer [aes_fi_vseq] Was Able to finish without clearing reset has 1 failures:
- Test aes_fi has 1 failures.
  - 45.aes_fi.26537477144802654079576768994464833188452635759653847634924896855732221473513
    Line 15186, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/45.aes_fi/latest/run.log
```
  UVM_FATAL @  69816827 ps: (aes_fi_vseq.sv:69) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.aes_fi_vseq] Was Able to finish without clearing reset
  UVM_INFO @  69816827 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```