AES/MASKED Simulation Results

Thursday August 01 2024 23:02:20 UTC

GitHub Revision: `625f353e9c`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 85273092133191575795496895645039765542965103003083525273509664765586668778052

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	114.813us	1	1	100.00
V1	smoke	aes_smoke	18.000s	2.240ms	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	58.397us	5	5	100.00
V1	csr_rw	aes_csr_rw	4.000s	64.616us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	9.000s	612.669us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	444.103us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	3.000s	125.390us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	4.000s	64.616us	20	20	100.00
		aes_csr_aliasing	5.000s	444.103us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	18.000s	2.240ms	50	50	100.00
		aes_config_error	1.167m	3.908ms	50	50	100.00
		aes_stress	19.000s	418.463us	50	50	100.00
V2	key_length	aes_smoke	18.000s	2.240ms	50	50	100.00
		aes_config_error	1.167m	3.908ms	50	50	100.00
		aes_stress	19.000s	418.463us	50	50	100.00
V2	back2back	aes_stress	19.000s	418.463us	50	50	100.00
		aes_b2b	1.083m	851.811us	50	50	100.00
V2	backpressure	aes_stress	19.000s	418.463us	50	50	100.00
V2	multi_message	aes_smoke	18.000s	2.240ms	50	50	100.00
		aes_config_error	1.167m	3.908ms	50	50	100.00
		aes_stress	19.000s	418.463us	50	50	100.00
		aes_alert_reset	25.000s	1.723ms	50	50	100.00
V2	failure_test	aes_man_cfg_err	5.000s	75.466us	50	50	100.00
		aes_config_error	1.167m	3.908ms	50	50	100.00
		aes_alert_reset	25.000s	1.723ms	50	50	100.00
V2	trigger_clear_test	aes_clear	59.000s	4.306ms	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	33.000s	2.353ms	1	1	100.00
V2	reset_recovery	aes_alert_reset	25.000s	1.723ms	50	50	100.00
V2	stress	aes_stress	19.000s	418.463us	50	50	100.00
V2	sideload	aes_stress	19.000s	418.463us	50	50	100.00
		aes_sideload	18.000s	996.517us	50	50	100.00
V2	deinitialization	aes_deinit	21.000s	623.241us	50	50	100.00
V2	stress_all	aes_stress_all	4.083m	8.618ms	10	10	100.00
V2	alert_test	aes_alert_test	4.000s	55.092us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	6.000s	436.987us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	6.000s	436.987us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	58.397us	5	5	100.00
		aes_csr_rw	4.000s	64.616us	20	20	100.00
		aes_csr_aliasing	5.000s	444.103us	5	5	100.00
		aes_same_csr_outstanding	4.000s	80.379us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	58.397us	5	5	100.00
		aes_csr_rw	4.000s	64.616us	20	20	100.00
		aes_csr_aliasing	5.000s	444.103us	5	5	100.00
		aes_same_csr_outstanding	4.000s	80.379us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	2.200m	4.415ms	50	50	100.00
V2S	fault_inject	aes_fi	34.000s	1.521ms	50	50	100.00
		aes_control_fi	51.000s	10.006ms	282	300	94.00
		aes_cipher_fi	43.000s	10.009ms	334	350	95.43
V2S	shadow_reg_update_error	aes_shadow_reg_errors	4.000s	113.921us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	4.000s	113.921us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	4.000s	113.921us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	4.000s	113.921us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	5.000s	706.463us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	9.000s	969.420us	5	5	100.00
		aes_tl_intg_err	6.000s	2.190ms	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	6.000s	2.190ms	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	25.000s	1.723ms	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	4.000s	113.921us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	18.000s	2.240ms	50	50	100.00
		aes_stress	19.000s	418.463us	50	50	100.00
		aes_alert_reset	25.000s	1.723ms	50	50	100.00
		aes_core_fi	1.450m	10.003ms	67	70	95.71
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	4.000s	113.921us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	7.000s	342.091us	50	50	100.00
		aes_stress	19.000s	418.463us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	19.000s	418.463us	50	50	100.00
		aes_sideload	18.000s	996.517us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	7.000s	342.091us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	7.000s	342.091us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	7.000s	342.091us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	7.000s	342.091us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	7.000s	342.091us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	19.000s	418.463us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	19.000s	418.463us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	34.000s	1.521ms	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	34.000s	1.521ms	50	50	100.00
		aes_control_fi	51.000s	10.006ms	282	300	94.00
		aes_cipher_fi	43.000s	10.009ms	334	350	95.43
		aes_ctr_fi	5.000s	106.513us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	34.000s	1.521ms	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	34.000s	1.521ms	50	50	100.00
		aes_control_fi	51.000s	10.006ms	282	300	94.00
		aes_cipher_fi	43.000s	10.009ms	334	350	95.43
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	43.000s	10.009ms	334	350	95.43
V2S	sec_cm_ctr_fsm_sparse	aes_fi	34.000s	1.521ms	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	34.000s	1.521ms	50	50	100.00
		aes_control_fi	51.000s	10.006ms	282	300	94.00
		aes_ctr_fi	5.000s	106.513us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	34.000s	1.521ms	50	50	100.00
		aes_control_fi	51.000s	10.006ms	282	300	94.00
		aes_cipher_fi	43.000s	10.009ms	334	350	95.43
		aes_ctr_fi	5.000s	106.513us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	25.000s	1.723ms	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	34.000s	1.521ms	50	50	100.00
		aes_control_fi	51.000s	10.006ms	282	300	94.00
		aes_cipher_fi	43.000s	10.009ms	334	350	95.43
		aes_ctr_fi	5.000s	106.513us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	34.000s	1.521ms	50	50	100.00
		aes_control_fi	51.000s	10.006ms	282	300	94.00
		aes_cipher_fi	43.000s	10.009ms	334	350	95.43
		aes_ctr_fi	5.000s	106.513us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	34.000s	1.521ms	50	50	100.00
		aes_control_fi	51.000s	10.006ms	282	300	94.00
		aes_ctr_fi	5.000s	106.513us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	34.000s	1.521ms	50	50	100.00
		aes_control_fi	51.000s	10.006ms	282	300	94.00
		aes_cipher_fi	43.000s	10.009ms	334	350	95.43
V2S		TOTAL			948	985	96.24
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	17.217m	38.807ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1555	1602	97.07

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	13	100.00
V2S	11	11	8	72.73
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.37	98.55	96.32	99.43	95.91	97.64	97.78	98.96	97.01

Failure Buckets

Job aes_masked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 17 failures:
- Test aes_control_fi has 11 failures.
  - 5.aes_control_fi.90858232377502091018975946538572602896650584003325670061438934954081329808213
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/5.aes_control_fi/latest/run.log
```
  Job ID: smart:e872ac62-3bb8-476e-b69b-482a565b4fdf
```
  - 6.aes_control_fi.89168155859830542646008194614289140508684588808018522936755153258968728376794
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/6.aes_control_fi/latest/run.log
```
  Job ID: smart:13a1593c-a70b-42f8-b576-07b8bb06499e
```
  - ... and 9 more failures.
- Test aes_cipher_fi has 6 failures.
  - 24.aes_cipher_fi.39994244113196850648115085341116117979684838438404332581268041050954262000887
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/24.aes_cipher_fi/latest/run.log
```
  Job ID: smart:b722d84b-e363-434e-b351-d10e2007d9f0
```
  - 90.aes_cipher_fi.38601858432814708041144833447714645351040239581760646812436154883690994579503
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/90.aes_cipher_fi/latest/run.log
```
  Job ID: smart:57438af7-2c9c-4857-8c87-517182a5fac2
```
  - ... and 4 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 10 failures:
- Test aes_cipher_fi has 10 failures.
  - 22.aes_cipher_fi.102677612835119886749654140523940895118481676407496561599155504364025623822414
    Line 319, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/22.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10033823562 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10033823562 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 89.aes_cipher_fi.45870144248365926514000943714839929823836717561024425127611985918567139461440
    Line 323, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/89.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10016390918 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10016390918 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 8 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues

has 7 failures:

Test aes_stress_all_with_rand_reset has 7 failures.

0.aes_stress_all_with_rand_reset.95253122791813693543184740665534408052746686450843043257858085996950585464372
Line 1522, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 7130737173 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 7130737173 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.90550135017198302567130197944864550669760478599557062394219029240075350828894
Line 820, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 38807225071 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 38807225071 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 6 failures:
- Test aes_control_fi has 6 failures.
  - 39.aes_control_fi.9143525916518452175446831019658545671990424296806908978783312510355746325345
    Line 313, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/39.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10009004078 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10009004078 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 97.aes_control_fi.95018102277234576700721372141484194148562480788141726393918301356610614793919
    Line 327, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/97.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10006107868 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006107868 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues

has 3 failures:

Test aes_stress_all_with_rand_reset has 3 failures.

3.aes_stress_all_with_rand_reset.5989822454859386062227898658195063280029491954087559291138932429858379408544
Line 636, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 261139043 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 261139043 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.aes_stress_all_with_rand_reset.58270072592789641803613557940894579570065870687394788049368880115197500018058
Line 1611, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/4.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 846602779 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 846602779 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 3 failures:
- Test aes_core_fi has 3 failures.
  - 5.aes_core_fi.41094430132551145603787286783874784556293196928582867824629693539399756868747
    Line 320, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/5.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10092307148 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10092307148 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 25.aes_core_fi.102906595756024241060524946297076117112447059613861083074108247634068978023147
    Line 322, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/25.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10056971916 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10056971916 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,993): Assertion AesSecCmDataRegLocalEscIv has failed (* cycles, starting * PS) has 1 failures:
- Test aes_control_fi has 1 failures.
  - 250.aes_control_fi.14273445843985266295913787671013188369629861048268436746378850837022291702514
    Line 309, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/250.aes_control_fi/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,993): (time 83660091 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 83535091 PS)
  UVM_ERROR @  83660091 ps: (aes_core.sv:993) [ASSERT FAILED] AesSecCmDataRegLocalEscIv
  UVM_INFO @  83660091 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```