AES/MASKED Simulation Results

Tuesday August 06 2024 23:02:29 UTC

GitHub Revision: `5fd4ecc0fc`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 56304622830272859824235340993951659280265419461975949533183046575604373639200

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	4.000s	64.960us	1	1	100.00
V1	smoke	aes_smoke	10.000s	91.526us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	75.134us	5	5	100.00
V1	csr_rw	aes_csr_rw	3.000s	98.770us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	11.000s	9.327ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	814.187us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	6.000s	74.472us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	3.000s	98.770us	20	20	100.00
		aes_csr_aliasing	5.000s	814.187us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	10.000s	91.526us	50	50	100.00
		aes_config_error	41.000s	2.334ms	50	50	100.00
		aes_stress	16.000s	397.247us	50	50	100.00
V2	key_length	aes_smoke	10.000s	91.526us	50	50	100.00
		aes_config_error	41.000s	2.334ms	50	50	100.00
		aes_stress	16.000s	397.247us	50	50	100.00
V2	back2back	aes_stress	16.000s	397.247us	50	50	100.00
		aes_b2b	58.000s	739.943us	50	50	100.00
V2	backpressure	aes_stress	16.000s	397.247us	50	50	100.00
V2	multi_message	aes_smoke	10.000s	91.526us	50	50	100.00
		aes_config_error	41.000s	2.334ms	50	50	100.00
		aes_stress	16.000s	397.247us	50	50	100.00
		aes_alert_reset	27.000s	2.419ms	50	50	100.00
V2	failure_test	aes_man_cfg_err	8.000s	250.918us	50	50	100.00
		aes_config_error	41.000s	2.334ms	50	50	100.00
		aes_alert_reset	27.000s	2.419ms	50	50	100.00
V2	trigger_clear_test	aes_clear	24.000s	768.350us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	18.000s	1.092ms	1	1	100.00
V2	reset_recovery	aes_alert_reset	27.000s	2.419ms	50	50	100.00
V2	stress	aes_stress	16.000s	397.247us	50	50	100.00
V2	sideload	aes_stress	16.000s	397.247us	50	50	100.00
		aes_sideload	41.000s	1.184ms	50	50	100.00
V2	deinitialization	aes_deinit	18.000s	634.076us	50	50	100.00
V2	stress_all	aes_stress_all	2.333m	6.166ms	10	10	100.00
V2	alert_test	aes_alert_test	8.000s	155.252us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	12.000s	2.279ms	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	12.000s	2.279ms	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	75.134us	5	5	100.00
		aes_csr_rw	3.000s	98.770us	20	20	100.00
		aes_csr_aliasing	5.000s	814.187us	5	5	100.00
		aes_same_csr_outstanding	8.000s	85.595us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	75.134us	5	5	100.00
		aes_csr_rw	3.000s	98.770us	20	20	100.00
		aes_csr_aliasing	5.000s	814.187us	5	5	100.00
		aes_same_csr_outstanding	8.000s	85.595us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	22.000s	889.147us	50	50	100.00
V2S	fault_inject	aes_fi	31.000s	1.149ms	50	50	100.00
		aes_control_fi	50.000s	10.005ms	273	300	91.00
		aes_cipher_fi	32.000s	10.278ms	337	350	96.29
V2S	shadow_reg_update_error	aes_shadow_reg_errors	8.000s	111.074us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	8.000s	111.074us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	8.000s	111.074us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	8.000s	111.074us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	8.000s	96.772us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	7.000s	1.074ms	5	5	100.00
		aes_tl_intg_err	9.000s	381.538us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	9.000s	381.538us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	27.000s	2.419ms	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	8.000s	111.074us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	10.000s	91.526us	50	50	100.00
		aes_stress	16.000s	397.247us	50	50	100.00
		aes_alert_reset	27.000s	2.419ms	50	50	100.00
		aes_core_fi	1.050m	3.880ms	70	70	100.00
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	8.000s	111.074us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	7.000s	94.502us	50	50	100.00
		aes_stress	16.000s	397.247us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	16.000s	397.247us	50	50	100.00
		aes_sideload	41.000s	1.184ms	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	7.000s	94.502us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	7.000s	94.502us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	7.000s	94.502us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	7.000s	94.502us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	7.000s	94.502us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	16.000s	397.247us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	16.000s	397.247us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	31.000s	1.149ms	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	31.000s	1.149ms	50	50	100.00
		aes_control_fi	50.000s	10.005ms	273	300	91.00
		aes_cipher_fi	32.000s	10.278ms	337	350	96.29
		aes_ctr_fi	8.000s	54.967us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	31.000s	1.149ms	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	31.000s	1.149ms	50	50	100.00
		aes_control_fi	50.000s	10.005ms	273	300	91.00
		aes_cipher_fi	32.000s	10.278ms	337	350	96.29
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	32.000s	10.278ms	337	350	96.29
V2S	sec_cm_ctr_fsm_sparse	aes_fi	31.000s	1.149ms	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	31.000s	1.149ms	50	50	100.00
		aes_control_fi	50.000s	10.005ms	273	300	91.00
		aes_ctr_fi	8.000s	54.967us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	31.000s	1.149ms	50	50	100.00
		aes_control_fi	50.000s	10.005ms	273	300	91.00
		aes_cipher_fi	32.000s	10.278ms	337	350	96.29
		aes_ctr_fi	8.000s	54.967us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	27.000s	2.419ms	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	31.000s	1.149ms	50	50	100.00
		aes_control_fi	50.000s	10.005ms	273	300	91.00
		aes_cipher_fi	32.000s	10.278ms	337	350	96.29
		aes_ctr_fi	8.000s	54.967us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	31.000s	1.149ms	50	50	100.00
		aes_control_fi	50.000s	10.005ms	273	300	91.00
		aes_cipher_fi	32.000s	10.278ms	337	350	96.29
		aes_ctr_fi	8.000s	54.967us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	31.000s	1.149ms	50	50	100.00
		aes_control_fi	50.000s	10.005ms	273	300	91.00
		aes_ctr_fi	8.000s	54.967us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	31.000s	1.149ms	50	50	100.00
		aes_control_fi	50.000s	10.005ms	273	300	91.00
		aes_cipher_fi	32.000s	10.278ms	337	350	96.29
V2S		TOTAL			945	985	95.94
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	6.733m	10.460ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1552	1602	96.88

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	13	100.00
V2S	11	11	9	81.82
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.28	98.48	96.16	99.40	95.69	97.72	100.00	98.96	95.41

Failure Buckets

Job aes_masked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 28 failures:
- Test aes_control_fi has 20 failures.
  - 51.aes_control_fi.22217233254396522053603797141226342776262503624124506624015069661764768360563
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/51.aes_control_fi/latest/run.log
```
  Job ID: smart:7727e029-106f-4d4c-82d2-5af547fd8fe3
```
  - 55.aes_control_fi.62843878457204685980371150875358672282119538134629180920362920863775230278512
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/55.aes_control_fi/latest/run.log
```
  Job ID: smart:2fa46db2-644e-466a-983e-4af76d690c9e
```
  - ... and 18 more failures.
- Test aes_cipher_fi has 8 failures.
  - 157.aes_cipher_fi.11462826715901991189411556971102649604347365943589877242296270675498526704538
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/157.aes_cipher_fi/latest/run.log
```
  Job ID: smart:a69fc07d-27f7-44ff-a941-e76898e5cce0
```
  - 163.aes_cipher_fi.64898826899971332447867512987300711872465220469599387150818364644893545215291
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/163.aes_cipher_fi/latest/run.log
```
  Job ID: smart:a323d958-ff73-42a6-bb6c-1a535e87eb4f
```
  - ... and 6 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 7 failures:
- Test aes_control_fi has 7 failures.
  - 32.aes_control_fi.105870658067379324861498669834623588408912918725261305344678008387778871374732
    Line 324, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/32.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10030408930 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10030408930 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 38.aes_control_fi.10686043717666362599546911141471759122406117762109394735609767004963121003933
    Line 316, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/38.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10004515484 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10004515484 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues

has 6 failures:

Test aes_stress_all_with_rand_reset has 6 failures.

0.aes_stress_all_with_rand_reset.46020466578243431739024034114865369074108218053845379595966249281292789080921
Line 668, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 640633650 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 640633650 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.aes_stress_all_with_rand_reset.23147724841191195561048664386196292919471533517081254989135172161110232833435
Line 1118, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 10460099059 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 10460099059 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 5 failures:
- Test aes_cipher_fi has 5 failures.
  - 122.aes_cipher_fi.56860475418983318345469858367148770925045139224113515041171160920581640568346
    Line 318, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/122.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10411395203 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10411395203 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 139.aes_cipher_fi.47148440572089327136115890171942449264672166899038154391496940416861980541562
    Line 324, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/139.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10025456640 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10025456640 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues

has 4 failures:

Test aes_stress_all_with_rand_reset has 4 failures.

1.aes_stress_all_with_rand_reset.104358987347188088151100741848115421793104612639894603175200451245457190373721
Line 1198, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2984138714 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 2984138714 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.aes_stress_all_with_rand_reset.73720921900615008888921596238133438096922332679572277672607403812788339413013
Line 668, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 281872963 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 281872963 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.