AES/MASKED Simulation Results

Wednesday August 07 2024 23:02:33 UTC

GitHub Revision: `bbf435ceff`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 6888687353677204195542416712589698377810102273194685652880785004967849651007

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	2.000s	107.078us	1	1	100.00
V1	smoke	aes_smoke	17.000s	98.004us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	69.525us	5	5	100.00
V1	csr_rw	aes_csr_rw	7.000s	83.273us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	10.000s	529.487us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	1.972ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	8.000s	73.587us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	7.000s	83.273us	20	20	100.00
		aes_csr_aliasing	5.000s	1.972ms	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	17.000s	98.004us	50	50	100.00
		aes_config_error	1.250m	2.733ms	50	50	100.00
		aes_stress	18.000s	654.535us	50	50	100.00
V2	key_length	aes_smoke	17.000s	98.004us	50	50	100.00
		aes_config_error	1.250m	2.733ms	50	50	100.00
		aes_stress	18.000s	654.535us	50	50	100.00
V2	back2back	aes_stress	18.000s	654.535us	50	50	100.00
		aes_b2b	41.000s	380.727us	50	50	100.00
V2	backpressure	aes_stress	18.000s	654.535us	50	50	100.00
V2	multi_message	aes_smoke	17.000s	98.004us	50	50	100.00
		aes_config_error	1.250m	2.733ms	50	50	100.00
		aes_stress	18.000s	654.535us	50	50	100.00
		aes_alert_reset	15.000s	200.821us	50	50	100.00
V2	failure_test	aes_man_cfg_err	9.000s	217.891us	50	50	100.00
		aes_config_error	1.250m	2.733ms	50	50	100.00
		aes_alert_reset	15.000s	200.821us	50	50	100.00
V2	trigger_clear_test	aes_clear	1.467m	2.931ms	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	14.000s	221.866us	1	1	100.00
V2	reset_recovery	aes_alert_reset	15.000s	200.821us	50	50	100.00
V2	stress	aes_stress	18.000s	654.535us	50	50	100.00
V2	sideload	aes_stress	18.000s	654.535us	50	50	100.00
		aes_sideload	13.000s	412.389us	50	50	100.00
V2	deinitialization	aes_deinit	17.000s	180.683us	50	50	100.00
V2	stress_all	aes_stress_all	10.117m	17.081ms	10	10	100.00
V2	alert_test	aes_alert_test	13.000s	72.318us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	11.000s	697.775us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	11.000s	697.775us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	69.525us	5	5	100.00
		aes_csr_rw	7.000s	83.273us	20	20	100.00
		aes_csr_aliasing	5.000s	1.972ms	5	5	100.00
		aes_same_csr_outstanding	4.000s	200.529us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	69.525us	5	5	100.00
		aes_csr_rw	7.000s	83.273us	20	20	100.00
		aes_csr_aliasing	5.000s	1.972ms	5	5	100.00
		aes_same_csr_outstanding	4.000s	200.529us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	3.033m	8.405ms	50	50	100.00
V2S	fault_inject	aes_fi	22.000s	94.527us	48	50	96.00
		aes_control_fi	47.000s	10.007ms	276	300	92.00
		aes_cipher_fi	48.000s	10.033ms	338	350	96.57
V2S	shadow_reg_update_error	aes_shadow_reg_errors	3.000s	117.557us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	3.000s	117.557us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	3.000s	117.557us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	3.000s	117.557us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	13.000s	79.048us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	13.000s	1.621ms	5	5	100.00
		aes_tl_intg_err	9.000s	4.407ms	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	9.000s	4.407ms	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	15.000s	200.821us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	3.000s	117.557us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	17.000s	98.004us	50	50	100.00
		aes_stress	18.000s	654.535us	50	50	100.00
		aes_alert_reset	15.000s	200.821us	50	50	100.00
		aes_core_fi	1.400m	10.024ms	67	70	95.71
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	3.000s	117.557us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	9.000s	51.953us	50	50	100.00
		aes_stress	18.000s	654.535us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	18.000s	654.535us	50	50	100.00
		aes_sideload	13.000s	412.389us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	9.000s	51.953us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	9.000s	51.953us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	9.000s	51.953us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	9.000s	51.953us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	9.000s	51.953us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	18.000s	654.535us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	18.000s	654.535us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	22.000s	94.527us	48	50	96.00
V2S	sec_cm_main_fsm_redun	aes_fi	22.000s	94.527us	48	50	96.00
		aes_control_fi	47.000s	10.007ms	276	300	92.00
		aes_cipher_fi	48.000s	10.033ms	338	350	96.57
		aes_ctr_fi	13.000s	89.014us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	22.000s	94.527us	48	50	96.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	22.000s	94.527us	48	50	96.00
		aes_control_fi	47.000s	10.007ms	276	300	92.00
		aes_cipher_fi	48.000s	10.033ms	338	350	96.57
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	48.000s	10.033ms	338	350	96.57
V2S	sec_cm_ctr_fsm_sparse	aes_fi	22.000s	94.527us	48	50	96.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	22.000s	94.527us	48	50	96.00
		aes_control_fi	47.000s	10.007ms	276	300	92.00
		aes_ctr_fi	13.000s	89.014us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	22.000s	94.527us	48	50	96.00
		aes_control_fi	47.000s	10.007ms	276	300	92.00
		aes_cipher_fi	48.000s	10.033ms	338	350	96.57
		aes_ctr_fi	13.000s	89.014us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	15.000s	200.821us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	22.000s	94.527us	48	50	96.00
		aes_control_fi	47.000s	10.007ms	276	300	92.00
		aes_cipher_fi	48.000s	10.033ms	338	350	96.57
		aes_ctr_fi	13.000s	89.014us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	22.000s	94.527us	48	50	96.00
		aes_control_fi	47.000s	10.007ms	276	300	92.00
		aes_cipher_fi	48.000s	10.033ms	338	350	96.57
		aes_ctr_fi	13.000s	89.014us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	22.000s	94.527us	48	50	96.00
		aes_control_fi	47.000s	10.007ms	276	300	92.00
		aes_ctr_fi	13.000s	89.014us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	22.000s	94.527us	48	50	96.00
		aes_control_fi	47.000s	10.007ms	276	300	92.00
		aes_cipher_fi	48.000s	10.033ms	338	350	96.57
V2S		TOTAL			944	985	95.84
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	4.800m	46.874ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1551	1602	96.82

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	13	100.00
V2S	11	11	7	63.64
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.37	98.57	96.37	99.45	95.78	97.72	100.00	99.11	96.41

Failure Buckets

Job aes_masked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 21 failures:
- Test aes_control_fi has 18 failures.
  - 3.aes_control_fi.111752404267981589952097668838538891849941748839702792996369209205348614285796
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/3.aes_control_fi/latest/run.log
```
  Job ID: smart:c1e2c599-b9d2-45c9-b5dd-dafc26c69681
```
  - 43.aes_control_fi.21946000113953391458753509688882180637602094658523491536430072426084993218548
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/43.aes_control_fi/latest/run.log
```
  Job ID: smart:8417e64d-c8cd-48f7-b0b1-2a26aa6d8a40
```
  - ... and 16 more failures.
- Test aes_cipher_fi has 3 failures.
  - 193.aes_cipher_fi.71819739427918769036917594529745967906074534254836359944270913954268216889134
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/193.aes_cipher_fi/latest/run.log
```
  Job ID: smart:da3361f1-0ee0-40ae-bc05-a5a9345d2515
```
  - 240.aes_cipher_fi.85645643940412511102003193061784430592923365023765084193049066425673312817002
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/240.aes_cipher_fi/latest/run.log
```
  Job ID: smart:5530ccbd-b82a-47dc-97d2-33a59e5bb971
```
  - ... and 1 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 9 failures:
- Test aes_cipher_fi has 9 failures.
  - 19.aes_cipher_fi.104771945193788058481009665666400951527720968504536711091200916093708382902541
    Line 314, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/19.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10013006555 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10013006555 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 33.aes_cipher_fi.19402639433886990339828228633117044684763724816730249170078115353685853606100
    Line 316, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/33.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10021457289 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10021457289 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 7 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues

has 6 failures:

Test aes_stress_all_with_rand_reset has 6 failures.

0.aes_stress_all_with_rand_reset.33006828117044958564602602062346086397913742827374141004261506255714567107432
Line 808, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 7480583894 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 7480583894 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.aes_stress_all_with_rand_reset.95991007753725953700593345084746451442201955130683641248269592941454306845642
Line 445, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 219864127 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 219864127 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 6 failures:
- Test aes_control_fi has 6 failures.
  - 7.aes_control_fi.75498684734528645679781445514731202011814531565724843683140251869522369616627
    Line 318, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/7.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10010278480 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10010278480 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 100.aes_control_fi.45196894428112712878087519688613244451831218890947331104510799226571222089749
    Line 322, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/100.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10007489414 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10007489414 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues

has 4 failures:

Test aes_stress_all_with_rand_reset has 4 failures.

1.aes_stress_all_with_rand_reset.84727633865837024946433046989677846018036053137449504249910046239613952332707
Line 721, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 536789710 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 536789710 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.aes_stress_all_with_rand_reset.79721345088204987373882403041223436296745074960133561490437834135566295445180
Line 1487, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 769518208 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 769518208 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 3 failures:
- Test aes_core_fi has 3 failures.
  - 14.aes_core_fi.1691724332010060942359170599038064983224396202411122128399752273469343032232
    Line 317, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/14.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10023915827 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10023915827 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 67.aes_core_fi.34633910967686893439529433025849377638541748121844118849697401154945625814533
    Line 319, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/67.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10019779149 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10019779149 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.

UVM_FATAL (aes_fi_vseq.sv:69) virtual_sequencer [aes_fi_vseq] Was Able to finish without clearing reset has 2 failures:

Test aes_fi has 2 failures.

5.aes_fi.4779425774717268359021602213396946314465506626356886322166809047328086001698
Line 7477, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/5.aes_fi/latest/run.log

  UVM_FATAL @ 118673885 ps: (aes_fi_vseq.sv:69) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.aes_fi_vseq] Was Able to finish without clearing reset
  UVM_INFO @ 118673885 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

44.aes_fi.63400079636950209187164329803871885040766904520799997847103092913711359734291
Line 19331, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/44.aes_fi/latest/run.log

  UVM_FATAL @ 262984484 ps: (aes_fi_vseq.sv:69) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.aes_fi_vseq] Was Able to finish without clearing reset
  UVM_INFO @ 262984484 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---