AES/MASKED Simulation Results

Thursday August 08 2024 23:02:08 UTC

GitHub Revision: `3707c48f56`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 96859198578252641766218135484681220968075710602306197013001824903089223290045

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	66.991us	1	1	100.00
V1	smoke	aes_smoke	10.000s	308.344us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	59.762us	5	5	100.00
V1	csr_rw	aes_csr_rw	7.000s	57.850us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	9.000s	182.655us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	4.000s	180.298us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	13.000s	166.284us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	7.000s	57.850us	20	20	100.00
		aes_csr_aliasing	4.000s	180.298us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	10.000s	308.344us	50	50	100.00
		aes_config_error	53.000s	6.691ms	50	50	100.00
		aes_stress	4.350m	6.997ms	50	50	100.00
V2	key_length	aes_smoke	10.000s	308.344us	50	50	100.00
		aes_config_error	53.000s	6.691ms	50	50	100.00
		aes_stress	4.350m	6.997ms	50	50	100.00
V2	back2back	aes_stress	4.350m	6.997ms	50	50	100.00
		aes_b2b	1.050m	702.708us	50	50	100.00
V2	backpressure	aes_stress	4.350m	6.997ms	50	50	100.00
V2	multi_message	aes_smoke	10.000s	308.344us	50	50	100.00
		aes_config_error	53.000s	6.691ms	50	50	100.00
		aes_stress	4.350m	6.997ms	50	50	100.00
		aes_alert_reset	22.000s	863.645us	50	50	100.00
V2	failure_test	aes_man_cfg_err	18.000s	386.493us	50	50	100.00
		aes_config_error	53.000s	6.691ms	50	50	100.00
		aes_alert_reset	22.000s	863.645us	50	50	100.00
V2	trigger_clear_test	aes_clear	22.000s	301.999us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	12.000s	617.432us	1	1	100.00
V2	reset_recovery	aes_alert_reset	22.000s	863.645us	50	50	100.00
V2	stress	aes_stress	4.350m	6.997ms	50	50	100.00
V2	sideload	aes_stress	4.350m	6.997ms	50	50	100.00
		aes_sideload	16.000s	503.738us	50	50	100.00
V2	deinitialization	aes_deinit	16.000s	449.942us	50	50	100.00
V2	stress_all	aes_stress_all	1.450m	1.380ms	10	10	100.00
V2	alert_test	aes_alert_test	8.000s	99.031us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	14.000s	245.980us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	14.000s	245.980us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	59.762us	5	5	100.00
		aes_csr_rw	7.000s	57.850us	20	20	100.00
		aes_csr_aliasing	4.000s	180.298us	5	5	100.00
		aes_same_csr_outstanding	4.000s	65.863us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	59.762us	5	5	100.00
		aes_csr_rw	7.000s	57.850us	20	20	100.00
		aes_csr_aliasing	4.000s	180.298us	5	5	100.00
		aes_same_csr_outstanding	4.000s	65.863us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	1.833m	3.590ms	50	50	100.00
V2S	fault_inject	aes_fi	34.000s	2.534ms	49	50	98.00
		aes_control_fi	51.000s	10.018ms	276	300	92.00
		aes_cipher_fi	50.000s	10.007ms	340	350	97.14
V2S	shadow_reg_update_error	aes_shadow_reg_errors	8.000s	82.940us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	8.000s	82.940us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	8.000s	82.940us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	8.000s	82.940us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	4.000s	415.905us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	21.000s	2.347ms	5	5	100.00
		aes_tl_intg_err	8.000s	129.083us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	8.000s	129.083us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	22.000s	863.645us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	8.000s	82.940us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	10.000s	308.344us	50	50	100.00
		aes_stress	4.350m	6.997ms	50	50	100.00
		aes_alert_reset	22.000s	863.645us	50	50	100.00
		aes_core_fi	1.117m	10.004ms	67	70	95.71
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	8.000s	82.940us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	11.000s	111.144us	49	50	98.00
		aes_stress	4.350m	6.997ms	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	4.350m	6.997ms	50	50	100.00
		aes_sideload	16.000s	503.738us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	11.000s	111.144us	49	50	98.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	11.000s	111.144us	49	50	98.00
V2S	sec_cm_key_sec_wipe	aes_readability	11.000s	111.144us	49	50	98.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	11.000s	111.144us	49	50	98.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	11.000s	111.144us	49	50	98.00
V2S	sec_cm_data_reg_key_sca	aes_stress	4.350m	6.997ms	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	4.350m	6.997ms	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	34.000s	2.534ms	49	50	98.00
V2S	sec_cm_main_fsm_redun	aes_fi	34.000s	2.534ms	49	50	98.00
		aes_control_fi	51.000s	10.018ms	276	300	92.00
		aes_cipher_fi	50.000s	10.007ms	340	350	97.14
		aes_ctr_fi	10.000s	207.373us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	34.000s	2.534ms	49	50	98.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	34.000s	2.534ms	49	50	98.00
		aes_control_fi	51.000s	10.018ms	276	300	92.00
		aes_cipher_fi	50.000s	10.007ms	340	350	97.14
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	50.000s	10.007ms	340	350	97.14
V2S	sec_cm_ctr_fsm_sparse	aes_fi	34.000s	2.534ms	49	50	98.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	34.000s	2.534ms	49	50	98.00
		aes_control_fi	51.000s	10.018ms	276	300	92.00
		aes_ctr_fi	10.000s	207.373us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	34.000s	2.534ms	49	50	98.00
		aes_control_fi	51.000s	10.018ms	276	300	92.00
		aes_cipher_fi	50.000s	10.007ms	340	350	97.14
		aes_ctr_fi	10.000s	207.373us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	22.000s	863.645us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	34.000s	2.534ms	49	50	98.00
		aes_control_fi	51.000s	10.018ms	276	300	92.00
		aes_cipher_fi	50.000s	10.007ms	340	350	97.14
		aes_ctr_fi	10.000s	207.373us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	34.000s	2.534ms	49	50	98.00
		aes_control_fi	51.000s	10.018ms	276	300	92.00
		aes_cipher_fi	50.000s	10.007ms	340	350	97.14
		aes_ctr_fi	10.000s	207.373us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	34.000s	2.534ms	49	50	98.00
		aes_control_fi	51.000s	10.018ms	276	300	92.00
		aes_ctr_fi	10.000s	207.373us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	34.000s	2.534ms	49	50	98.00
		aes_control_fi	51.000s	10.018ms	276	300	92.00
		aes_cipher_fi	50.000s	10.007ms	340	350	97.14
V2S		TOTAL			946	985	96.04
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	5.867m	148.045ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1553	1602	96.94

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	13	100.00
V2S	11	11	6	54.55
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.34	98.55	96.32	99.43	95.69	97.72	98.52	98.96	96.61

Failure Buckets

Job aes_masked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 21 failures:
- Test aes_control_fi has 14 failures.
  - 6.aes_control_fi.18030833426926773736087570877428184292951580570440266111749512075682006959768
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/6.aes_control_fi/latest/run.log
```
  Job ID: smart:fe447461-241e-48d0-a2aa-edda2ef67628
```
  - 13.aes_control_fi.10746569263420659615837622005500541621251028399015313704390646502916802961712
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/13.aes_control_fi/latest/run.log
```
  Job ID: smart:bda1f7ec-3b2b-4f04-8b44-3e2292d7ffd0
```
  - ... and 12 more failures.
- Test aes_cipher_fi has 7 failures.
  - 19.aes_cipher_fi.71033709162961261688390614475054339938123870092692351453617418489022779374961
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/19.aes_cipher_fi/latest/run.log
```
  Job ID: smart:9aea816e-5b63-487d-ad9b-f5b9ded162c1
```
  - 87.aes_cipher_fi.33429833289496980542415367012535473733084364029085043725426945303214227638213
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/87.aes_cipher_fi/latest/run.log
```
  Job ID: smart:85e1af9d-bc1d-4cdb-aa9d-6a739b1c1161
```
  - ... and 5 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 10 failures:

Test aes_stress_all_with_rand_reset has 10 failures.

0.aes_stress_all_with_rand_reset.25929270287939551934561693151477452042583396718343808298465491973810099815382
Line 1498, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1697961628 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1697961628 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.2330428563830734565678950682474562530091863884168616794346573686068426177975
Line 695, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 20901390879 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 20901390879 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 8 more failures.

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 10 failures:
- Test aes_control_fi has 10 failures.
  - 27.aes_control_fi.114887624274899081129059113533577552359711135889165188075653773041916740323863
    Line 332, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/27.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10007661742 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10007661742 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 83.aes_control_fi.9156629749252185687643909008444022268855744053980814077785540724066331966122
    Line 316, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/83.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10007631357 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10007631357 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 8 more failures.
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 3 failures:
- Test aes_core_fi has 3 failures.
  - 28.aes_core_fi.102447687225860517444226346118304000509681301344060370887608395385100185268214
    Line 318, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/28.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10003645030 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10003645030 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 29.aes_core_fi.107600745126120452193684053808929815754138123842017584963003854797111918610873
    Line 321, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/29.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10010140124 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10010140124 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 3 failures:
- Test aes_cipher_fi has 3 failures.
  - 104.aes_cipher_fi.63371379367638981547723462790662028454878469573112749348939568083006654464539
    Line 317, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/104.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10012201091 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10012201091 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 301.aes_cipher_fi.5841904943970190837484414685224203772922606831942419133052325468318777215054
    Line 317, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/301.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10006561329 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006561329 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,993): Assertion AesSecCmDataRegLocalEscIv has failed (* cycles, starting * PS) has 1 failures:
- Test aes_fi has 1 failures.
  - 27.aes_fi.44524754231358636080048995407198105644100451298138125792915561057608027850186
    Line 1010, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/27.aes_fi/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,993): (time 13291268 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 13251268 PS)
  UVM_ERROR @  13291268 ps: (aes_core.sv:993) [ASSERT FAILED] AesSecCmDataRegLocalEscIv
  UVM_INFO @  13291268 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_readability_vseq.sv:114) virtual_sequencer [aes_readability_vseq] ----| Data reg was did not clear |---- has 1 failures:
- Test aes_readability has 1 failures.
  - 29.aes_readability.87720463757895388731930847895713675042755736018523880646334181799837458152683
    Line 307, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/29.aes_readability/latest/run.log
```
  UVM_FATAL @   7020488 ps: (aes_readability_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.aes_readability_vseq] ----| Data reg was did not clear |----
  UVM_INFO @   7020488 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```