AES/MASKED Simulation Results

Friday August 09 2024 23:02:07 UTC

GitHub Revision: `07b417ef03`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 39866585070056138360117926942905553094756411441088058786676399955088054585836

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	105.466us	1	1	100.00
V1	smoke	aes_smoke	11.000s	1.165ms	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	4.000s	114.148us	5	5	100.00
V1	csr_rw	aes_csr_rw	18.000s	52.389us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	9.000s	329.400us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	160.117us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	13.000s	122.752us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	18.000s	52.389us	20	20	100.00
		aes_csr_aliasing	5.000s	160.117us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	11.000s	1.165ms	50	50	100.00
		aes_config_error	17.000s	495.788us	50	50	100.00
		aes_stress	13.000s	1.730ms	50	50	100.00
V2	key_length	aes_smoke	11.000s	1.165ms	50	50	100.00
		aes_config_error	17.000s	495.788us	50	50	100.00
		aes_stress	13.000s	1.730ms	50	50	100.00
V2	back2back	aes_stress	13.000s	1.730ms	50	50	100.00
		aes_b2b	53.000s	1.177ms	50	50	100.00
V2	backpressure	aes_stress	13.000s	1.730ms	50	50	100.00
V2	multi_message	aes_smoke	11.000s	1.165ms	50	50	100.00
		aes_config_error	17.000s	495.788us	50	50	100.00
		aes_stress	13.000s	1.730ms	50	50	100.00
		aes_alert_reset	20.000s	697.469us	50	50	100.00
V2	failure_test	aes_man_cfg_err	5.000s	74.631us	50	50	100.00
		aes_config_error	17.000s	495.788us	50	50	100.00
		aes_alert_reset	20.000s	697.469us	50	50	100.00
V2	trigger_clear_test	aes_clear	6.367m	9.495ms	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	18.000s	757.945us	1	1	100.00
V2	reset_recovery	aes_alert_reset	20.000s	697.469us	50	50	100.00
V2	stress	aes_stress	13.000s	1.730ms	50	50	100.00
V2	sideload	aes_stress	13.000s	1.730ms	50	50	100.00
		aes_sideload	9.000s	241.849us	50	50	100.00
V2	deinitialization	aes_deinit	1.467m	3.237ms	50	50	100.00
V2	stress_all	aes_stress_all	4.217m	10.799ms	10	10	100.00
V2	alert_test	aes_alert_test	4.000s	147.930us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	14.000s	187.619us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	14.000s	187.619us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	4.000s	114.148us	5	5	100.00
		aes_csr_rw	18.000s	52.389us	20	20	100.00
		aes_csr_aliasing	5.000s	160.117us	5	5	100.00
		aes_same_csr_outstanding	9.000s	863.791us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	4.000s	114.148us	5	5	100.00
		aes_csr_rw	18.000s	52.389us	20	20	100.00
		aes_csr_aliasing	5.000s	160.117us	5	5	100.00
		aes_same_csr_outstanding	9.000s	863.791us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	1.517m	2.998ms	50	50	100.00
V2S	fault_inject	aes_fi	1.133m	3.519ms	49	50	98.00
		aes_control_fi	49.000s	10.007ms	273	300	91.00
		aes_cipher_fi	47.000s	10.162ms	334	350	95.43
V2S	shadow_reg_update_error	aes_shadow_reg_errors	15.000s	55.971us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	15.000s	55.971us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	15.000s	55.971us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	15.000s	55.971us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	13.000s	95.161us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	1.450m	8.809ms	5	5	100.00
		aes_tl_intg_err	9.000s	137.067us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	9.000s	137.067us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	20.000s	697.469us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	15.000s	55.971us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	11.000s	1.165ms	50	50	100.00
		aes_stress	13.000s	1.730ms	50	50	100.00
		aes_alert_reset	20.000s	697.469us	50	50	100.00
		aes_core_fi	1.367m	10.009ms	68	70	97.14
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	15.000s	55.971us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	4.000s	69.884us	50	50	100.00
		aes_stress	13.000s	1.730ms	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	13.000s	1.730ms	50	50	100.00
		aes_sideload	9.000s	241.849us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	4.000s	69.884us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	4.000s	69.884us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	4.000s	69.884us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	4.000s	69.884us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	4.000s	69.884us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	13.000s	1.730ms	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	13.000s	1.730ms	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	1.133m	3.519ms	49	50	98.00
V2S	sec_cm_main_fsm_redun	aes_fi	1.133m	3.519ms	49	50	98.00
		aes_control_fi	49.000s	10.007ms	273	300	91.00
		aes_cipher_fi	47.000s	10.162ms	334	350	95.43
		aes_ctr_fi	6.000s	164.576us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	1.133m	3.519ms	49	50	98.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	1.133m	3.519ms	49	50	98.00
		aes_control_fi	49.000s	10.007ms	273	300	91.00
		aes_cipher_fi	47.000s	10.162ms	334	350	95.43
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	47.000s	10.162ms	334	350	95.43
V2S	sec_cm_ctr_fsm_sparse	aes_fi	1.133m	3.519ms	49	50	98.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	1.133m	3.519ms	49	50	98.00
		aes_control_fi	49.000s	10.007ms	273	300	91.00
		aes_ctr_fi	6.000s	164.576us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	1.133m	3.519ms	49	50	98.00
		aes_control_fi	49.000s	10.007ms	273	300	91.00
		aes_cipher_fi	47.000s	10.162ms	334	350	95.43
		aes_ctr_fi	6.000s	164.576us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	20.000s	697.469us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	1.133m	3.519ms	49	50	98.00
		aes_control_fi	49.000s	10.007ms	273	300	91.00
		aes_cipher_fi	47.000s	10.162ms	334	350	95.43
		aes_ctr_fi	6.000s	164.576us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	1.133m	3.519ms	49	50	98.00
		aes_control_fi	49.000s	10.007ms	273	300	91.00
		aes_cipher_fi	47.000s	10.162ms	334	350	95.43
		aes_ctr_fi	6.000s	164.576us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	1.133m	3.519ms	49	50	98.00
		aes_control_fi	49.000s	10.007ms	273	300	91.00
		aes_ctr_fi	6.000s	164.576us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	1.133m	3.519ms	49	50	98.00
		aes_control_fi	49.000s	10.007ms	273	300	91.00
		aes_cipher_fi	47.000s	10.162ms	334	350	95.43
V2S		TOTAL			939	985	95.33
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	49.000s	819.340us	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1546	1602	96.50

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	13	100.00
V2S	11	11	7	63.64
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.32	98.53	96.25	99.43	95.61	97.72	97.78	98.96	96.81

Failure Buckets

Job aes_masked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 30 failures:
- Test aes_cipher_fi has 12 failures.
  - 13.aes_cipher_fi.78705355530540386696346435401362815900857296553153114774303008041602528598179
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/13.aes_cipher_fi/latest/run.log
```
  Job ID: smart:9ae5419e-2b4b-4359-8c52-aef0c3e51de7
```
  - 26.aes_cipher_fi.22779360470516030714819016766333362877182249441951734293476118848323381433556
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/26.aes_cipher_fi/latest/run.log
```
  Job ID: smart:d3ec4de2-d29a-4ea3-81df-f6124219d233
```
  - ... and 10 more failures.
- Test aes_control_fi has 18 failures.
  - 20.aes_control_fi.68059231389972526273072217068006976381047636162227809227752522680428002031106
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/20.aes_control_fi/latest/run.log
```
  Job ID: smart:8edbc1f1-c77e-4d70-b7cf-5ff2852093d5
```
  - 24.aes_control_fi.98779311685903595741582264041178108045693513435441425572485366074777040994200
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/24.aes_control_fi/latest/run.log
```
  Job ID: smart:1d6c4154-d221-48ad-a41f-cc296ab89fe4
```
  - ... and 16 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 9 failures:
- Test aes_control_fi has 9 failures.
  - 9.aes_control_fi.96919257273801687024136732943681262759044424590717891717139525143334826307284
    Line 323, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/9.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10017391856 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10017391856 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 23.aes_control_fi.105317582368580859805083005707625773877611309454227701718032195045490276075868
    Line 325, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/23.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10014775164 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10014775164 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 7 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 5 failures:

Test aes_stress_all_with_rand_reset has 5 failures.

1.aes_stress_all_with_rand_reset.54430929977766019077158944111039554035956308813744394336141186328714503676439
Line 758, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 370912531 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 370912531 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.aes_stress_all_with_rand_reset.97727378909833620708081869160376896623334153922342381313429573700795388088284
Line 884, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 5269547147 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 5269547147 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 4 failures:

Test aes_stress_all_with_rand_reset has 4 failures.

0.aes_stress_all_with_rand_reset.34187878716111665962753773361985151084236897399203283590526360778433786793882
Line 485, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 773068240 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 773068240 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.aes_stress_all_with_rand_reset.102711026765329222618100939918749508839099635924393479912762448875748766241148
Line 620, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1041179120 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1041179120 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 4 failures:
- Test aes_cipher_fi has 4 failures.
  - 35.aes_cipher_fi.71466416155669328423494928351751742182381020334662906458145258853184474439205
    Line 321, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/35.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10019657524 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10019657524 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 59.aes_cipher_fi.30161720766699103363669690278648392077825745725513166473634545351698915813398
    Line 316, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/59.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10014374885 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10014374885 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_core_fi has 2 failures.
  - 17.aes_core_fi.85835703261543235058904660716737467002593497287393679060601686573338525175271
    Line 321, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/17.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10019122613 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10019122613 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 44.aes_core_fi.91319435062493081145947368197190609638677927779222171434207672248710287217737
    Line 323, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/44.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10008909328 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10008909328 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:837) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 4.aes_stress_all_with_rand_reset.107384211361856419439784272138834088486929016614071120661373267297135762661490
    Line 335, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/4.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 819339773 ps: (cip_base_vseq.sv:837) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 819339773 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_fi_vseq.sv:69) virtual_sequencer [aes_fi_vseq] Was Able to finish without clearing reset has 1 failures:
- Test aes_fi has 1 failures.
  - 6.aes_fi.25456385686821859972744379673144349581954293304890299701201041564360150397661
    Line 13035, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/6.aes_fi/latest/run.log
```
  UVM_FATAL @ 325118434 ps: (aes_fi_vseq.sv:69) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.aes_fi_vseq] Was Able to finish without clearing reset
  UVM_INFO @ 325118434 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```