AES/MASKED Simulation Results

Saturday August 10 2024 23:02:23 UTC

GitHub Revision: `07b417ef03`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 2196818177928134427831197337249851347498377272679561983541244979366753055772

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	63.380us	1	1	100.00
V1	smoke	aes_smoke	13.000s	77.485us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	105.597us	5	5	100.00
V1	csr_rw	aes_csr_rw	5.000s	80.577us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	10.000s	970.784us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	90.327us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	4.000s	169.725us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	5.000s	80.577us	20	20	100.00
		aes_csr_aliasing	5.000s	90.327us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	13.000s	77.485us	50	50	100.00
		aes_config_error	14.000s	1.253ms	50	50	100.00
		aes_stress	30.000s	917.979us	50	50	100.00
V2	key_length	aes_smoke	13.000s	77.485us	50	50	100.00
		aes_config_error	14.000s	1.253ms	50	50	100.00
		aes_stress	30.000s	917.979us	50	50	100.00
V2	back2back	aes_stress	30.000s	917.979us	50	50	100.00
		aes_b2b	30.000s	1.081ms	50	50	100.00
V2	backpressure	aes_stress	30.000s	917.979us	50	50	100.00
V2	multi_message	aes_smoke	13.000s	77.485us	50	50	100.00
		aes_config_error	14.000s	1.253ms	50	50	100.00
		aes_stress	30.000s	917.979us	50	50	100.00
		aes_alert_reset	25.000s	1.411ms	50	50	100.00
V2	failure_test	aes_man_cfg_err	29.000s	79.038us	50	50	100.00
		aes_config_error	14.000s	1.253ms	50	50	100.00
		aes_alert_reset	25.000s	1.411ms	50	50	100.00
V2	trigger_clear_test	aes_clear	43.000s	5.646ms	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	25.000s	1.348ms	1	1	100.00
V2	reset_recovery	aes_alert_reset	25.000s	1.411ms	50	50	100.00
V2	stress	aes_stress	30.000s	917.979us	50	50	100.00
V2	sideload	aes_stress	30.000s	917.979us	50	50	100.00
		aes_sideload	28.000s	1.030ms	50	50	100.00
V2	deinitialization	aes_deinit	11.000s	171.177us	50	50	100.00
V2	stress_all	aes_stress_all	2.800m	5.917ms	10	10	100.00
V2	alert_test	aes_alert_test	9.000s	66.925us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	6.000s	474.712us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	6.000s	474.712us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	105.597us	5	5	100.00
		aes_csr_rw	5.000s	80.577us	20	20	100.00
		aes_csr_aliasing	5.000s	90.327us	5	5	100.00
		aes_same_csr_outstanding	4.000s	122.555us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	105.597us	5	5	100.00
		aes_csr_rw	5.000s	80.577us	20	20	100.00
		aes_csr_aliasing	5.000s	90.327us	5	5	100.00
		aes_same_csr_outstanding	4.000s	122.555us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	35.000s	3.908ms	50	50	100.00
V2S	fault_inject	aes_fi	2.233m	6.631ms	50	50	100.00
		aes_control_fi	48.000s	10.005ms	281	300	93.67
		aes_cipher_fi	50.000s	10.018ms	339	350	96.86
V2S	shadow_reg_update_error	aes_shadow_reg_errors	3.000s	73.822us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	3.000s	73.822us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	3.000s	73.822us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	3.000s	73.822us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	4.000s	511.051us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	17.000s	2.291ms	5	5	100.00
		aes_tl_intg_err	5.000s	306.698us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	5.000s	306.698us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	25.000s	1.411ms	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	3.000s	73.822us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	13.000s	77.485us	50	50	100.00
		aes_stress	30.000s	917.979us	50	50	100.00
		aes_alert_reset	25.000s	1.411ms	50	50	100.00
		aes_core_fi	1.517m	10.017ms	68	70	97.14
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	3.000s	73.822us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	9.000s	61.269us	50	50	100.00
		aes_stress	30.000s	917.979us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	30.000s	917.979us	50	50	100.00
		aes_sideload	28.000s	1.030ms	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	9.000s	61.269us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	9.000s	61.269us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	9.000s	61.269us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	9.000s	61.269us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	9.000s	61.269us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	30.000s	917.979us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	30.000s	917.979us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	2.233m	6.631ms	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	2.233m	6.631ms	50	50	100.00
		aes_control_fi	48.000s	10.005ms	281	300	93.67
		aes_cipher_fi	50.000s	10.018ms	339	350	96.86
		aes_ctr_fi	18.000s	64.048us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	2.233m	6.631ms	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	2.233m	6.631ms	50	50	100.00
		aes_control_fi	48.000s	10.005ms	281	300	93.67
		aes_cipher_fi	50.000s	10.018ms	339	350	96.86
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	50.000s	10.018ms	339	350	96.86
V2S	sec_cm_ctr_fsm_sparse	aes_fi	2.233m	6.631ms	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	2.233m	6.631ms	50	50	100.00
		aes_control_fi	48.000s	10.005ms	281	300	93.67
		aes_ctr_fi	18.000s	64.048us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	2.233m	6.631ms	50	50	100.00
		aes_control_fi	48.000s	10.005ms	281	300	93.67
		aes_cipher_fi	50.000s	10.018ms	339	350	96.86
		aes_ctr_fi	18.000s	64.048us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	25.000s	1.411ms	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	2.233m	6.631ms	50	50	100.00
		aes_control_fi	48.000s	10.005ms	281	300	93.67
		aes_cipher_fi	50.000s	10.018ms	339	350	96.86
		aes_ctr_fi	18.000s	64.048us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	2.233m	6.631ms	50	50	100.00
		aes_control_fi	48.000s	10.005ms	281	300	93.67
		aes_cipher_fi	50.000s	10.018ms	339	350	96.86
		aes_ctr_fi	18.000s	64.048us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	2.233m	6.631ms	50	50	100.00
		aes_control_fi	48.000s	10.005ms	281	300	93.67
		aes_ctr_fi	18.000s	64.048us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	2.233m	6.631ms	50	50	100.00
		aes_control_fi	48.000s	10.005ms	281	300	93.67
		aes_cipher_fi	50.000s	10.018ms	339	350	96.86
V2S		TOTAL			953	985	96.75
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	1.467m	21.602ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1560	1602	97.38

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	13	100.00
V2S	11	11	8	72.73
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.34	98.54	96.30	99.42	95.78	97.72	97.78	98.96	96.81

Failure Buckets

Job aes_masked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 19 failures:
- Test aes_cipher_fi has 6 failures.
  - 11.aes_cipher_fi.39050132595445325636389516622832304994706005645141425785264521072178005773026
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/11.aes_cipher_fi/latest/run.log
```
  Job ID: smart:8fad1c37-9dc9-423d-9c10-b5c275cda7d1
```
  - 74.aes_cipher_fi.83922501726179153094543583604785298736556147602683388866545232410345508972831
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/74.aes_cipher_fi/latest/run.log
```
  Job ID: smart:624f614f-c600-4e48-bd6b-a3a3188d86cd
```
  - ... and 4 more failures.
- Test aes_control_fi has 13 failures.
  - 43.aes_control_fi.48849541404534560752637308005047735573735011303655359862640376728148687534102
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/43.aes_control_fi/latest/run.log
```
  Job ID: smart:586fc51a-0cdd-4056-8e0d-b8c18e4bc777
```
  - 120.aes_control_fi.63593335823348630153431631497450013453236126695268988264636509767473232237790
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/120.aes_control_fi/latest/run.log
```
  Job ID: smart:4bfaf18a-a892-4f09-b8be-e5872495a397
```
  - ... and 11 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues

has 7 failures:

Test aes_stress_all_with_rand_reset has 7 failures.

0.aes_stress_all_with_rand_reset.69528466838910395445011696967759595178100067861083434088219004125385196969707
Line 1504, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 6655858591 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 6655858591 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.aes_stress_all_with_rand_reset.13003357852043741146753832172252315620149003453696336474084136491757406016245
Line 1455, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2721533453 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 2721533453 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 6 failures:
- Test aes_control_fi has 6 failures.
  - 88.aes_control_fi.115163644847058967911567902556165176033527220925786176430431714635774419433195
    Line 315, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/88.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10004973540 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10004973540 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 134.aes_control_fi.95951831386292877804319197488505130987311712094217608772082208914751694996603
    Line 318, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/134.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10026031265 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10026031265 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 5 failures:
- Test aes_cipher_fi has 5 failures.
  - 133.aes_cipher_fi.96388952710764712748973114548701270809710706673087079211847530040821671772811
    Line 315, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/133.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10085423196 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10085423196 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 176.aes_cipher_fi.100620232603186358812245419554531892640849435268122697560040794069975945147229
    Line 314, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/176.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10007283136 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10007283136 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues

has 3 failures:

Test aes_stress_all_with_rand_reset has 3 failures.

1.aes_stress_all_with_rand_reset.38917191647905667753355341832158702901977396056530299414615998096249351944477
Line 737, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 3299194573 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 3299194573 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.aes_stress_all_with_rand_reset.78035732083271786708960879680793023222493418003216412470581520516665846726237
Line 1374, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 4064137590 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 4064137590 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_core_fi has 2 failures.
  - 3.aes_core_fi.8918988255590384509664700711345995784986434457609816854957983898716799764765
    Line 313, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/3.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10017058664 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10017058664 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 63.aes_core_fi.976871411066063689800473686414462227055484509760672569665543786485933880573
    Line 321, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/63.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10093884741 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10093884741 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```