AES/MASKED Simulation Results

Friday August 16 2024 23:02:10 UTC

GitHub Revision: `76588857da`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 107397868712693014844033025164446565408841343499325418676943424680076749785789

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	104.445us	1	1	100.00
V1	smoke	aes_smoke	15.000s	158.439us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	4.000s	60.418us	5	5	100.00
V1	csr_rw	aes_csr_rw	4.000s	110.265us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	11.000s	794.267us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	132.450us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	4.000s	99.153us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	4.000s	110.265us	20	20	100.00
		aes_csr_aliasing	5.000s	132.450us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	15.000s	158.439us	50	50	100.00
		aes_config_error	16.000s	528.073us	50	50	100.00
		aes_stress	52.000s	2.065ms	50	50	100.00
V2	key_length	aes_smoke	15.000s	158.439us	50	50	100.00
		aes_config_error	16.000s	528.073us	50	50	100.00
		aes_stress	52.000s	2.065ms	50	50	100.00
V2	back2back	aes_stress	52.000s	2.065ms	50	50	100.00
		aes_b2b	41.000s	527.928us	50	50	100.00
V2	backpressure	aes_stress	52.000s	2.065ms	50	50	100.00
V2	multi_message	aes_smoke	15.000s	158.439us	50	50	100.00
		aes_config_error	16.000s	528.073us	50	50	100.00
		aes_stress	52.000s	2.065ms	50	50	100.00
		aes_alert_reset	12.000s	119.094us	50	50	100.00
V2	failure_test	aes_man_cfg_err	18.000s	68.411us	50	50	100.00
		aes_config_error	16.000s	528.073us	50	50	100.00
		aes_alert_reset	12.000s	119.094us	50	50	100.00
V2	trigger_clear_test	aes_clear	37.000s	2.360ms	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	10.000s	660.083us	1	1	100.00
V2	reset_recovery	aes_alert_reset	12.000s	119.094us	50	50	100.00
V2	stress	aes_stress	52.000s	2.065ms	50	50	100.00
V2	sideload	aes_stress	52.000s	2.065ms	50	50	100.00
		aes_sideload	31.000s	789.567us	50	50	100.00
V2	deinitialization	aes_deinit	18.000s	793.798us	50	50	100.00
V2	stress_all	aes_stress_all	1.317m	1.446ms	10	10	100.00
V2	alert_test	aes_alert_test	13.000s	134.670us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	6.000s	452.418us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	6.000s	452.418us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	4.000s	60.418us	5	5	100.00
		aes_csr_rw	4.000s	110.265us	20	20	100.00
		aes_csr_aliasing	5.000s	132.450us	5	5	100.00
		aes_same_csr_outstanding	5.000s	353.593us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	4.000s	60.418us	5	5	100.00
		aes_csr_rw	4.000s	110.265us	20	20	100.00
		aes_csr_aliasing	5.000s	132.450us	5	5	100.00
		aes_same_csr_outstanding	5.000s	353.593us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	49.000s	1.496ms	50	50	100.00
V2S	fault_inject	aes_fi	16.000s	900.508us	49	50	98.00
		aes_control_fi	27.000s	10.016ms	278	300	92.67
		aes_cipher_fi	52.000s	10.009ms	336	350	96.00
V2S	shadow_reg_update_error	aes_shadow_reg_errors	4.000s	158.686us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	4.000s	158.686us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	4.000s	158.686us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	4.000s	158.686us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	4.000s	256.130us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	10.000s	607.150us	5	5	100.00
		aes_tl_intg_err	5.000s	488.634us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	5.000s	488.634us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	12.000s	119.094us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	4.000s	158.686us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	15.000s	158.439us	50	50	100.00
		aes_stress	52.000s	2.065ms	50	50	100.00
		aes_alert_reset	12.000s	119.094us	50	50	100.00
		aes_core_fi	1.433m	10.011ms	69	70	98.57
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	4.000s	158.686us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	15.000s	57.180us	50	50	100.00
		aes_stress	52.000s	2.065ms	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	52.000s	2.065ms	50	50	100.00
		aes_sideload	31.000s	789.567us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	15.000s	57.180us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	15.000s	57.180us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	15.000s	57.180us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	15.000s	57.180us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	15.000s	57.180us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	52.000s	2.065ms	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	52.000s	2.065ms	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	16.000s	900.508us	49	50	98.00
V2S	sec_cm_main_fsm_redun	aes_fi	16.000s	900.508us	49	50	98.00
		aes_control_fi	27.000s	10.016ms	278	300	92.67
		aes_cipher_fi	52.000s	10.009ms	336	350	96.00
		aes_ctr_fi	13.000s	46.943us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	16.000s	900.508us	49	50	98.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	16.000s	900.508us	49	50	98.00
		aes_control_fi	27.000s	10.016ms	278	300	92.67
		aes_cipher_fi	52.000s	10.009ms	336	350	96.00
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	52.000s	10.009ms	336	350	96.00
V2S	sec_cm_ctr_fsm_sparse	aes_fi	16.000s	900.508us	49	50	98.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	16.000s	900.508us	49	50	98.00
		aes_control_fi	27.000s	10.016ms	278	300	92.67
		aes_ctr_fi	13.000s	46.943us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	16.000s	900.508us	49	50	98.00
		aes_control_fi	27.000s	10.016ms	278	300	92.67
		aes_cipher_fi	52.000s	10.009ms	336	350	96.00
		aes_ctr_fi	13.000s	46.943us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	12.000s	119.094us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	16.000s	900.508us	49	50	98.00
		aes_control_fi	27.000s	10.016ms	278	300	92.67
		aes_cipher_fi	52.000s	10.009ms	336	350	96.00
		aes_ctr_fi	13.000s	46.943us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	16.000s	900.508us	49	50	98.00
		aes_control_fi	27.000s	10.016ms	278	300	92.67
		aes_cipher_fi	52.000s	10.009ms	336	350	96.00
		aes_ctr_fi	13.000s	46.943us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	16.000s	900.508us	49	50	98.00
		aes_control_fi	27.000s	10.016ms	278	300	92.67
		aes_ctr_fi	13.000s	46.943us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	16.000s	900.508us	49	50	98.00
		aes_control_fi	27.000s	10.016ms	278	300	92.67
		aes_cipher_fi	52.000s	10.009ms	336	350	96.00
V2S		TOTAL			947	985	96.14
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	58.000s	3.177ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1554	1602	97.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	13	100.00
V2S	11	11	7	63.64
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.34	98.54	96.30	99.42	95.83	97.64	97.04	98.96	96.21

Failure Buckets

Job aes_masked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 25 failures:
- Test aes_cipher_fi has 7 failures.
  - 28.aes_cipher_fi.32334698043215683283601835650774008845087103735526592215044521836904639134155
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/28.aes_cipher_fi/latest/run.log
```
  Job ID: smart:d1286608-d0c3-4950-a3dc-c622a2cadd36
```
  - 29.aes_cipher_fi.101231673142283322032828250266931295584578449613386944796990503532133068873645
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/29.aes_cipher_fi/latest/run.log
```
  Job ID: smart:bbe39b8c-d7dd-4ddb-a304-3d6817645ab4
```
  - ... and 5 more failures.
- Test aes_control_fi has 18 failures.
  - 34.aes_control_fi.89284347636591972547132468807831402474017166020538045389870260272384419012861
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/34.aes_control_fi/latest/run.log
```
  Job ID: smart:3ca731ad-4dfa-4997-9401-6818eb577985
```
  - 60.aes_control_fi.37487652490297345108213885169523472830280157827198156438365158899340168607796
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/60.aes_control_fi/latest/run.log
```
  Job ID: smart:a6398e03-2924-4c5e-b3f3-fa6183614f36
```
  - ... and 16 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 7 failures:
- Test aes_cipher_fi has 7 failures.
  - 49.aes_cipher_fi.17225198308851759568301268358116732438223351252368071021463268324128337267487
    Line 321, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/49.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10014200082 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10014200082 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 83.aes_cipher_fi.39082830261324905570699707224495988198483673473266206929727679149378609479143
    Line 319, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/83.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10013511015 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10013511015 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 5 failures:

Test aes_stress_all_with_rand_reset has 5 failures.

1.aes_stress_all_with_rand_reset.53026130213654716718074204045127034550988340227562470830316439821115769195019
Line 868, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 728967369 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 728967369 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.aes_stress_all_with_rand_reset.88012195539454075614935100220270378050556846144328176159805901460050574767969
Line 1562, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/4.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 3176988509 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 3176988509 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 4 failures:
- Test aes_control_fi has 4 failures.
  - 102.aes_control_fi.26007745445747277152963841425291730658708568870988624546071333444409740838970
    Line 327, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/102.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10016170414 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10016170414 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 177.aes_control_fi.98874179026163999908597689688164682499983945379375226350634781754660546560431
    Line 321, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/177.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10064709638 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10064709638 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
UVM_ERROR (cip_base_vseq.sv:868) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 3 failures:
- Test aes_stress_all_with_rand_reset has 3 failures.
  - 0.aes_stress_all_with_rand_reset.38469380632183980750174082434172360753164075981486583474179858421919411436182
    Line 470, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 789396953 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 789396953 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.aes_stress_all_with_rand_reset.110442971508156187629780624892938218682589721806392016158758286754566894138409
    Line 572, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 623694267 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 623694267 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 3.aes_stress_all_with_rand_reset.37686566076092220699919416183272245159547210871310782783439928060308476144623
    Line 1229, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 599799595 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 599799595 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_alert_reset_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 6.aes_stress_all_with_rand_reset.87119460483837193194509827389673079866113846502097209711565753089784581727144
    Line 322, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/6.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  34489440 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @  34489440 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 31.aes_core_fi.10929113100572581426932279671707289931940086686506428137943559504659643502685
    Line 324, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/31.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10011180576 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10011180576 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,987): Assertion AesSecCmDataRegLocalEscDataOut has failed (* cycles, starting * PS) has 1 failures:
- Test aes_fi has 1 failures.
  - 40.aes_fi.102871306772318579448389499585881685980304520236719537911914490011736440156651
    Line 3336, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/40.aes_fi/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,987): (time 11938827 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 11923902 PS)
  UVM_ERROR @  11938827 ps: (aes_core.sv:987) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut
  UVM_INFO @  11938827 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```