AES/MASKED Simulation Results

Tuesday August 13 2024 23:04:47 UTC

GitHub Revision: `098010d125`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 12185085088694708177096441863424670920996379189869351644310607217057882846251

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	79.398us	1	1	100.00
V1	smoke	aes_smoke	24.000s	4.453ms	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	111.815us	5	5	100.00
V1	csr_rw	aes_csr_rw	3.000s	117.698us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	11.000s	790.977us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	1.191ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	3.000s	78.379us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	3.000s	117.698us	20	20	100.00
		aes_csr_aliasing	5.000s	1.191ms	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	24.000s	4.453ms	50	50	100.00
		aes_config_error	20.000s	2.412ms	50	50	100.00
		aes_stress	3.000m	4.818ms	50	50	100.00
V2	key_length	aes_smoke	24.000s	4.453ms	50	50	100.00
		aes_config_error	20.000s	2.412ms	50	50	100.00
		aes_stress	3.000m	4.818ms	50	50	100.00
V2	back2back	aes_stress	3.000m	4.818ms	50	50	100.00
		aes_b2b	1.917m	1.434ms	50	50	100.00
V2	backpressure	aes_stress	3.000m	4.818ms	50	50	100.00
V2	multi_message	aes_smoke	24.000s	4.453ms	50	50	100.00
		aes_config_error	20.000s	2.412ms	50	50	100.00
		aes_stress	3.000m	4.818ms	50	50	100.00
		aes_alert_reset	38.000s	1.690ms	50	50	100.00
V2	failure_test	aes_man_cfg_err	9.000s	56.676us	50	50	100.00
		aes_config_error	20.000s	2.412ms	50	50	100.00
		aes_alert_reset	38.000s	1.690ms	50	50	100.00
V2	trigger_clear_test	aes_clear	2.833m	4.734ms	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	13.000s	1.501ms	1	1	100.00
V2	reset_recovery	aes_alert_reset	38.000s	1.690ms	50	50	100.00
V2	stress	aes_stress	3.000m	4.818ms	50	50	100.00
V2	sideload	aes_stress	3.000m	4.818ms	50	50	100.00
		aes_sideload	11.000s	956.237us	50	50	100.00
V2	deinitialization	aes_deinit	58.000s	1.975ms	50	50	100.00
V2	stress_all	aes_stress_all	2.400m	5.893ms	10	10	100.00
V2	alert_test	aes_alert_test	8.000s	59.234us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	6.000s	319.135us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	6.000s	319.135us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	111.815us	5	5	100.00
		aes_csr_rw	3.000s	117.698us	20	20	100.00
		aes_csr_aliasing	5.000s	1.191ms	5	5	100.00
		aes_same_csr_outstanding	4.000s	108.621us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	111.815us	5	5	100.00
		aes_csr_rw	3.000s	117.698us	20	20	100.00
		aes_csr_aliasing	5.000s	1.191ms	5	5	100.00
		aes_same_csr_outstanding	4.000s	108.621us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	12.000s	360.275us	50	50	100.00
V2S	fault_inject	aes_fi	17.000s	660.228us	50	50	100.00
		aes_control_fi	46.000s	10.007ms	283	300	94.33
		aes_cipher_fi	50.000s	10.016ms	341	350	97.43
V2S	shadow_reg_update_error	aes_shadow_reg_errors	3.000s	76.493us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	3.000s	76.493us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	3.000s	76.493us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	3.000s	76.493us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	4.000s	107.223us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	16.000s	1.861ms	5	5	100.00
		aes_tl_intg_err	5.000s	154.143us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	5.000s	154.143us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	38.000s	1.690ms	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	3.000s	76.493us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	24.000s	4.453ms	50	50	100.00
		aes_stress	3.000m	4.818ms	50	50	100.00
		aes_alert_reset	38.000s	1.690ms	50	50	100.00
		aes_core_fi	39.000s	10.007ms	69	70	98.57
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	3.000s	76.493us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	10.000s	497.811us	50	50	100.00
		aes_stress	3.000m	4.818ms	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	3.000m	4.818ms	50	50	100.00
		aes_sideload	11.000s	956.237us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	10.000s	497.811us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	10.000s	497.811us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	10.000s	497.811us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	10.000s	497.811us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	10.000s	497.811us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	3.000m	4.818ms	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	3.000m	4.818ms	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	17.000s	660.228us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	17.000s	660.228us	50	50	100.00
		aes_control_fi	46.000s	10.007ms	283	300	94.33
		aes_cipher_fi	50.000s	10.016ms	341	350	97.43
		aes_ctr_fi	8.000s	59.271us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	17.000s	660.228us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	17.000s	660.228us	50	50	100.00
		aes_control_fi	46.000s	10.007ms	283	300	94.33
		aes_cipher_fi	50.000s	10.016ms	341	350	97.43
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	50.000s	10.016ms	341	350	97.43
V2S	sec_cm_ctr_fsm_sparse	aes_fi	17.000s	660.228us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	17.000s	660.228us	50	50	100.00
		aes_control_fi	46.000s	10.007ms	283	300	94.33
		aes_ctr_fi	8.000s	59.271us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	17.000s	660.228us	50	50	100.00
		aes_control_fi	46.000s	10.007ms	283	300	94.33
		aes_cipher_fi	50.000s	10.016ms	341	350	97.43
		aes_ctr_fi	8.000s	59.271us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	38.000s	1.690ms	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	17.000s	660.228us	50	50	100.00
		aes_control_fi	46.000s	10.007ms	283	300	94.33
		aes_cipher_fi	50.000s	10.016ms	341	350	97.43
		aes_ctr_fi	8.000s	59.271us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	17.000s	660.228us	50	50	100.00
		aes_control_fi	46.000s	10.007ms	283	300	94.33
		aes_cipher_fi	50.000s	10.016ms	341	350	97.43
		aes_ctr_fi	8.000s	59.271us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	17.000s	660.228us	50	50	100.00
		aes_control_fi	46.000s	10.007ms	283	300	94.33
		aes_ctr_fi	8.000s	59.271us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	17.000s	660.228us	50	50	100.00
		aes_control_fi	46.000s	10.007ms	283	300	94.33
		aes_cipher_fi	50.000s	10.016ms	341	350	97.43
V2S		TOTAL			958	985	97.26
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	1.150m	2.514ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1565	1602	97.69

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	13	100.00
V2S	11	11	8	72.73
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.33	98.54	96.30	99.42	95.71	97.72	97.78	98.96	96.61

Failure Buckets

Job aes_masked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 13 failures:
- Test aes_control_fi has 10 failures.
  - 45.aes_control_fi.14024244122411834770649960826354039913276378200552558098734682161902593359683
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/45.aes_control_fi/latest/run.log
```
  Job ID: smart:95fa4568-5f09-4954-bd8f-b769159d34a4
```
  - 58.aes_control_fi.42997192946853922762872913526384784040313692973147118112072475083538714191483
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/58.aes_control_fi/latest/run.log
```
  Job ID: smart:02635685-7220-456f-afe7-271f66a1416e
```
  - ... and 8 more failures.
- Test aes_cipher_fi has 3 failures.
  - 180.aes_cipher_fi.106569835501252235741961942081832994970347225202686524150213547853739116615165
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/180.aes_cipher_fi/latest/run.log
```
  Job ID: smart:684238e3-a82a-48ac-953f-eb2c9ed23b55
```
  - 185.aes_cipher_fi.7865564383891886408941625781792553073789074386035875172978497309652584864080
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/185.aes_cipher_fi/latest/run.log
```
  Job ID: smart:c7a5620a-09dd-4190-ba2c-4cbaeb2f3447
```
  - ... and 1 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 7 failures:
- Test aes_control_fi has 7 failures.
  - 20.aes_control_fi.106290036642791655051809087190920777050204767125126261663211314488037111167732
    Line 324, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/20.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10036370662 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10036370662 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 27.aes_control_fi.110026953828637818344012062947087407152864508884691727882369706176948736954594
    Line 312, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/27.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10007123093 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10007123093 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 6 failures:

Test aes_stress_all_with_rand_reset has 6 failures.

0.aes_stress_all_with_rand_reset.98317814417139314559474362140235104100773964850601840548918123473848562824652
Line 363, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 157852755 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 157852755 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.aes_stress_all_with_rand_reset.43198274066769686053560728227118620441900081280160607390396324796810857689662
Line 1368, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 768588501 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 768588501 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 6 failures:
- Test aes_cipher_fi has 6 failures.
  - 42.aes_cipher_fi.94464118667477603226144174829251546172168140565029609076332477080535037374852
    Line 329, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/42.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10015732730 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10015732730 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 99.aes_cipher_fi.64518260667520354881662043491194470608533922243136938804092421333517924896221
    Line 324, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/99.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10028739998 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10028739998 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.
UVM_FATAL (aes_base_vseq.sv:74) [aes_reseed_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 2 failures:
- Test aes_stress_all_with_rand_reset has 2 failures.
  - 8.aes_stress_all_with_rand_reset.86843814643833519127632292714152168917989576527924897838752502993027989834218
    Line 1096, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/8.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 5409927166 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 5409927166 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 9.aes_stress_all_with_rand_reset.27071540390156803443142474829431074308513447647963301582898847828138049287092
    Line 326, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/9.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 296627126 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 296627126 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 1.aes_stress_all_with_rand_reset.94891207722933767860091728688549402214848027765817365485131021987202550250318
    Line 949, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 860062713 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 860062713 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:868) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 7.aes_stress_all_with_rand_reset.74555238588974308892999679589256983276438146873421081772333199713960670322661
    Line 535, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/7.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2293022408 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2293022408 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 31.aes_core_fi.100809107578392119885510427136240463380805987886165992780668750785340985832711
    Line 319, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/31.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10007282417 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10007282417 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```