AES/MASKED Simulation Results

Monday August 12 2024 23:02:30 UTC

GitHub Revision: `c082b8981f`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 107262934208806092150901079363789224644653433402469901409990667510497383888850

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	4.000s	61.902us	1	1	100.00
V1	smoke	aes_smoke	12.000s	182.837us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	89.632us	5	5	100.00
V1	csr_rw	aes_csr_rw	3.000s	67.823us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	11.000s	2.598ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	575.126us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	4.000s	134.366us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	3.000s	67.823us	20	20	100.00
		aes_csr_aliasing	5.000s	575.126us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	12.000s	182.837us	50	50	100.00
		aes_config_error	56.000s	1.838ms	50	50	100.00
		aes_stress	2.783m	6.096ms	50	50	100.00
V2	key_length	aes_smoke	12.000s	182.837us	50	50	100.00
		aes_config_error	56.000s	1.838ms	50	50	100.00
		aes_stress	2.783m	6.096ms	50	50	100.00
V2	back2back	aes_stress	2.783m	6.096ms	50	50	100.00
		aes_b2b	44.000s	609.965us	50	50	100.00
V2	backpressure	aes_stress	2.783m	6.096ms	50	50	100.00
V2	multi_message	aes_smoke	12.000s	182.837us	50	50	100.00
		aes_config_error	56.000s	1.838ms	50	50	100.00
		aes_stress	2.783m	6.096ms	50	50	100.00
		aes_alert_reset	1.050m	2.264ms	50	50	100.00
V2	failure_test	aes_man_cfg_err	9.000s	65.543us	50	50	100.00
		aes_config_error	56.000s	1.838ms	50	50	100.00
		aes_alert_reset	1.050m	2.264ms	50	50	100.00
V2	trigger_clear_test	aes_clear	42.000s	2.097ms	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	6.617m	24.512ms	1	1	100.00
V2	reset_recovery	aes_alert_reset	1.050m	2.264ms	50	50	100.00
V2	stress	aes_stress	2.783m	6.096ms	50	50	100.00
V2	sideload	aes_stress	2.783m	6.096ms	50	50	100.00
		aes_sideload	16.000s	586.535us	50	50	100.00
V2	deinitialization	aes_deinit	23.000s	1.429ms	50	50	100.00
V2	stress_all	aes_stress_all	14.883m	35.254ms	10	10	100.00
V2	alert_test	aes_alert_test	12.000s	64.687us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	6.000s	1.548ms	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	6.000s	1.548ms	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	89.632us	5	5	100.00
		aes_csr_rw	3.000s	67.823us	20	20	100.00
		aes_csr_aliasing	5.000s	575.126us	5	5	100.00
		aes_same_csr_outstanding	5.000s	550.963us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	89.632us	5	5	100.00
		aes_csr_rw	3.000s	67.823us	20	20	100.00
		aes_csr_aliasing	5.000s	575.126us	5	5	100.00
		aes_same_csr_outstanding	5.000s	550.963us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	1.883m	8.155ms	50	50	100.00
V2S	fault_inject	aes_fi	16.000s	366.271us	50	50	100.00
		aes_control_fi	49.000s	10.008ms	278	300	92.67
		aes_cipher_fi	51.000s	10.008ms	333	350	95.14
V2S	shadow_reg_update_error	aes_shadow_reg_errors	3.000s	84.185us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	3.000s	84.185us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	3.000s	84.185us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	3.000s	84.185us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	4.000s	155.050us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	11.000s	929.814us	5	5	100.00
		aes_tl_intg_err	5.000s	325.599us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	5.000s	325.599us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	1.050m	2.264ms	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	3.000s	84.185us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	12.000s	182.837us	50	50	100.00
		aes_stress	2.783m	6.096ms	50	50	100.00
		aes_alert_reset	1.050m	2.264ms	50	50	100.00
		aes_core_fi	14.000s	170.234us	69	70	98.57
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	3.000s	84.185us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	10.000s	112.535us	49	50	98.00
		aes_stress	2.783m	6.096ms	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	2.783m	6.096ms	50	50	100.00
		aes_sideload	16.000s	586.535us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	10.000s	112.535us	49	50	98.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	10.000s	112.535us	49	50	98.00
V2S	sec_cm_key_sec_wipe	aes_readability	10.000s	112.535us	49	50	98.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	10.000s	112.535us	49	50	98.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	10.000s	112.535us	49	50	98.00
V2S	sec_cm_data_reg_key_sca	aes_stress	2.783m	6.096ms	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	2.783m	6.096ms	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	16.000s	366.271us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	16.000s	366.271us	50	50	100.00
		aes_control_fi	49.000s	10.008ms	278	300	92.67
		aes_cipher_fi	51.000s	10.008ms	333	350	95.14
		aes_ctr_fi	13.000s	82.008us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	16.000s	366.271us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	16.000s	366.271us	50	50	100.00
		aes_control_fi	49.000s	10.008ms	278	300	92.67
		aes_cipher_fi	51.000s	10.008ms	333	350	95.14
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	51.000s	10.008ms	333	350	95.14
V2S	sec_cm_ctr_fsm_sparse	aes_fi	16.000s	366.271us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	16.000s	366.271us	50	50	100.00
		aes_control_fi	49.000s	10.008ms	278	300	92.67
		aes_ctr_fi	13.000s	82.008us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	16.000s	366.271us	50	50	100.00
		aes_control_fi	49.000s	10.008ms	278	300	92.67
		aes_cipher_fi	51.000s	10.008ms	333	350	95.14
		aes_ctr_fi	13.000s	82.008us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	1.050m	2.264ms	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	16.000s	366.271us	50	50	100.00
		aes_control_fi	49.000s	10.008ms	278	300	92.67
		aes_cipher_fi	51.000s	10.008ms	333	350	95.14
		aes_ctr_fi	13.000s	82.008us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	16.000s	366.271us	50	50	100.00
		aes_control_fi	49.000s	10.008ms	278	300	92.67
		aes_cipher_fi	51.000s	10.008ms	333	350	95.14
		aes_ctr_fi	13.000s	82.008us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	16.000s	366.271us	50	50	100.00
		aes_control_fi	49.000s	10.008ms	278	300	92.67
		aes_ctr_fi	13.000s	82.008us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	16.000s	366.271us	50	50	100.00
		aes_control_fi	49.000s	10.008ms	278	300	92.67
		aes_cipher_fi	51.000s	10.008ms	333	350	95.14
V2S		TOTAL			944	985	95.84
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	36.000s	1.049ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1551	1602	96.82

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	13	100.00
V2S	11	11	7	63.64
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.40	98.60	96.44	99.45	95.91	97.72	100.00	98.96	96.61

Failure Buckets

Job aes_masked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 24 failures:
- Test aes_control_fi has 16 failures.
  - 2.aes_control_fi.104196204122341845693293238723873963717528012744327100716253791372714187593069
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/2.aes_control_fi/latest/run.log
```
  Job ID: smart:caf2aa58-365e-40ff-8205-3865d2300c09
```
  - 25.aes_control_fi.87201727730036067449035197849722091569545627890016750721259412734864527533505
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/25.aes_control_fi/latest/run.log
```
  Job ID: smart:e5994540-5083-4486-84e2-3f8eef68dae5
```
  - ... and 14 more failures.
- Test aes_cipher_fi has 8 failures.
  - 90.aes_cipher_fi.113016887788992942744927223967502370251371424360761049439417392874033280162249
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/90.aes_cipher_fi/latest/run.log
```
  Job ID: smart:6616e7fe-0353-407c-a74f-ff40403a593d
```
  - 114.aes_cipher_fi.38885206063290389204671583549115666844684299792627577760042717693619970706442
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/114.aes_cipher_fi/latest/run.log
```
  Job ID: smart:6f0b07f8-d7c3-4a08-832a-4c204554ff35
```
  - ... and 6 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 9 failures:
- Test aes_cipher_fi has 9 failures.
  - 45.aes_cipher_fi.16947187511384628312131927479136627102226474595052730656054952569282580235306
    Line 322, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/45.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10008190860 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10008190860 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 64.aes_cipher_fi.106969865923711723822310070623167120008861425531143578369313629312363229384673
    Line 324, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/64.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10010027337 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10010027337 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 7 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 6 failures:
- Test aes_control_fi has 6 failures.
  - 83.aes_control_fi.80041385098739920565635506878957410741763275629483792770284644276535208743821
    Line 320, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/83.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10021834709 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10021834709 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 93.aes_control_fi.42653914225607024154794999776788973398488108707408237899805461148907117069890
    Line 325, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/93.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10011583510 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10011583510 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 5 failures:

Test aes_stress_all_with_rand_reset has 5 failures.

0.aes_stress_all_with_rand_reset.24518190364986317928968588424610212762120157188884094420024055423006320180438
Line 579, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 905203624 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 905203624 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.64391626453571625002106924961669745683590012271409102893748913129033716853975
Line 1135, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1049144877 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1049144877 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_FATAL (aes_base_vseq.sv:74) [aes_alert_reset_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 2.aes_stress_all_with_rand_reset.24772029393741381898295046238246197222226774004686306984415515403097499008618
    Line 330, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 258425707 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 258425707 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_reseed_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 3.aes_stress_all_with_rand_reset.91591251506903012057185846960583618429963000813415330336484079722182956285194
    Line 591, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 495845524 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 495845524 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: aes_reg_block.status reset value: * has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 5.aes_stress_all_with_rand_reset.61537342328420059780994330337167808724030309479085391053339597437426008715722
    Line 339, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/5.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  11316951 ps: (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (64 [0x40] vs 0 [0x0]) Regname: aes_reg_block.status reset value: 0x0
  UVM_INFO @  11316951 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 6.aes_stress_all_with_rand_reset.13303830057145980561005013352476861609603064653381092019559790554770495796210
    Line 877, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/6.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 4006319634 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 4006319634 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_stress_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 7.aes_stress_all_with_rand_reset.99725562769774736463761935959206690956974938446049445912042641875929837307477
    Line 321, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/7.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  57800519 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_stress_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @  57800519 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_readability_vseq.sv:114) virtual_sequencer [aes_readability_vseq] ----| Data reg was did not clear |---- has 1 failures:
- Test aes_readability has 1 failures.
  - 25.aes_readability.38019226301546723591796504820875434169952022955214467846248488027433814343658
    Line 308, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/25.aes_readability/latest/run.log
```
  UVM_FATAL @  16037115 ps: (aes_readability_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.aes_readability_vseq] ----| Data reg was did not clear |----
  UVM_INFO @  16037115 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 50.aes_core_fi.101344555883681568515511302700351464041679467406605461579612672153918314353602
    Line 314, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/50.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10051356743 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10051356743 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```