AES/MASKED Simulation Results

Monday August 12 2024 23:02:30 UTC

GitHub Revision: c082b8981f

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 107262934208806092150901079363789224644653433402469901409990667510497383888850

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 wake_up aes_wake_up 4.000s 61.902us 1 1 100.00
V1 smoke aes_smoke 12.000s 182.837us 50 50 100.00
V1 csr_hw_reset aes_csr_hw_reset 3.000s 89.632us 5 5 100.00
V1 csr_rw aes_csr_rw 3.000s 67.823us 20 20 100.00
V1 csr_bit_bash aes_csr_bit_bash 11.000s 2.598ms 5 5 100.00
V1 csr_aliasing aes_csr_aliasing 5.000s 575.126us 5 5 100.00
V1 csr_mem_rw_with_rand_reset aes_csr_mem_rw_with_rand_reset 4.000s 134.366us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr aes_csr_rw 3.000s 67.823us 20 20 100.00
aes_csr_aliasing 5.000s 575.126us 5 5 100.00
V1 TOTAL 106 106 100.00
V2 algorithm aes_smoke 12.000s 182.837us 50 50 100.00
aes_config_error 56.000s 1.838ms 50 50 100.00
aes_stress 2.783m 6.096ms 50 50 100.00
V2 key_length aes_smoke 12.000s 182.837us 50 50 100.00
aes_config_error 56.000s 1.838ms 50 50 100.00
aes_stress 2.783m 6.096ms 50 50 100.00
V2 back2back aes_stress 2.783m 6.096ms 50 50 100.00
aes_b2b 44.000s 609.965us 50 50 100.00
V2 backpressure aes_stress 2.783m 6.096ms 50 50 100.00
V2 multi_message aes_smoke 12.000s 182.837us 50 50 100.00
aes_config_error 56.000s 1.838ms 50 50 100.00
aes_stress 2.783m 6.096ms 50 50 100.00
aes_alert_reset 1.050m 2.264ms 50 50 100.00
V2 failure_test aes_man_cfg_err 9.000s 65.543us 50 50 100.00
aes_config_error 56.000s 1.838ms 50 50 100.00
aes_alert_reset 1.050m 2.264ms 50 50 100.00
V2 trigger_clear_test aes_clear 42.000s 2.097ms 50 50 100.00
V2 nist_test_vectors aes_nist_vectors 6.617m 24.512ms 1 1 100.00
V2 reset_recovery aes_alert_reset 1.050m 2.264ms 50 50 100.00
V2 stress aes_stress 2.783m 6.096ms 50 50 100.00
V2 sideload aes_stress 2.783m 6.096ms 50 50 100.00
aes_sideload 16.000s 586.535us 50 50 100.00
V2 deinitialization aes_deinit 23.000s 1.429ms 50 50 100.00
V2 stress_all aes_stress_all 14.883m 35.254ms 10 10 100.00
V2 alert_test aes_alert_test 12.000s 64.687us 50 50 100.00
V2 tl_d_oob_addr_access aes_tl_errors 6.000s 1.548ms 20 20 100.00
V2 tl_d_illegal_access aes_tl_errors 6.000s 1.548ms 20 20 100.00
V2 tl_d_outstanding_access aes_csr_hw_reset 3.000s 89.632us 5 5 100.00
aes_csr_rw 3.000s 67.823us 20 20 100.00
aes_csr_aliasing 5.000s 575.126us 5 5 100.00
aes_same_csr_outstanding 5.000s 550.963us 20 20 100.00
V2 tl_d_partial_access aes_csr_hw_reset 3.000s 89.632us 5 5 100.00
aes_csr_rw 3.000s 67.823us 20 20 100.00
aes_csr_aliasing 5.000s 575.126us 5 5 100.00
aes_same_csr_outstanding 5.000s 550.963us 20 20 100.00
V2 TOTAL 501 501 100.00
V2S reseeding aes_reseed 1.883m 8.155ms 50 50 100.00
V2S fault_inject aes_fi 16.000s 366.271us 50 50 100.00
aes_control_fi 49.000s 10.008ms 278 300 92.67
aes_cipher_fi 51.000s 10.008ms 333 350 95.14
V2S shadow_reg_update_error aes_shadow_reg_errors 3.000s 84.185us 20 20 100.00
V2S shadow_reg_read_clear_staged_value aes_shadow_reg_errors 3.000s 84.185us 20 20 100.00
V2S shadow_reg_storage_error aes_shadow_reg_errors 3.000s 84.185us 20 20 100.00
V2S shadowed_reset_glitch aes_shadow_reg_errors 3.000s 84.185us 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw aes_shadow_reg_errors_with_csr_rw 4.000s 155.050us 20 20 100.00
V2S tl_intg_err aes_sec_cm 11.000s 929.814us 5 5 100.00
aes_tl_intg_err 5.000s 325.599us 20 20 100.00
V2S sec_cm_bus_integrity aes_tl_intg_err 5.000s 325.599us 20 20 100.00
V2S sec_cm_lc_escalate_en_intersig_mubi aes_alert_reset 1.050m 2.264ms 50 50 100.00
V2S sec_cm_main_config_shadow aes_shadow_reg_errors 3.000s 84.185us 20 20 100.00
V2S sec_cm_main_config_sparse aes_smoke 12.000s 182.837us 50 50 100.00
aes_stress 2.783m 6.096ms 50 50 100.00
aes_alert_reset 1.050m 2.264ms 50 50 100.00
aes_core_fi 14.000s 170.234us 69 70 98.57
V2S sec_cm_aux_config_shadow aes_shadow_reg_errors 3.000s 84.185us 20 20 100.00
V2S sec_cm_aux_config_regwen aes_readability 10.000s 112.535us 49 50 98.00
aes_stress 2.783m 6.096ms 50 50 100.00
V2S sec_cm_key_sideload aes_stress 2.783m 6.096ms 50 50 100.00
aes_sideload 16.000s 586.535us 50 50 100.00
V2S sec_cm_key_sw_unreadable aes_readability 10.000s 112.535us 49 50 98.00
V2S sec_cm_data_reg_sw_unreadable aes_readability 10.000s 112.535us 49 50 98.00
V2S sec_cm_key_sec_wipe aes_readability 10.000s 112.535us 49 50 98.00
V2S sec_cm_iv_config_sec_wipe aes_readability 10.000s 112.535us 49 50 98.00
V2S sec_cm_data_reg_sec_wipe aes_readability 10.000s 112.535us 49 50 98.00
V2S sec_cm_data_reg_key_sca aes_stress 2.783m 6.096ms 50 50 100.00
V2S sec_cm_key_masking aes_stress 2.783m 6.096ms 50 50 100.00
V2S sec_cm_main_fsm_sparse aes_fi 16.000s 366.271us 50 50 100.00
V2S sec_cm_main_fsm_redun aes_fi 16.000s 366.271us 50 50 100.00
aes_control_fi 49.000s 10.008ms 278 300 92.67
aes_cipher_fi 51.000s 10.008ms 333 350 95.14
aes_ctr_fi 13.000s 82.008us 50 50 100.00
V2S sec_cm_cipher_fsm_sparse aes_fi 16.000s 366.271us 50 50 100.00
V2S sec_cm_cipher_fsm_redun aes_fi 16.000s 366.271us 50 50 100.00
aes_control_fi 49.000s 10.008ms 278 300 92.67
aes_cipher_fi 51.000s 10.008ms 333 350 95.14
V2S sec_cm_cipher_ctr_redun aes_cipher_fi 51.000s 10.008ms 333 350 95.14
V2S sec_cm_ctr_fsm_sparse aes_fi 16.000s 366.271us 50 50 100.00
V2S sec_cm_ctr_fsm_redun aes_fi 16.000s 366.271us 50 50 100.00
aes_control_fi 49.000s 10.008ms 278 300 92.67
aes_ctr_fi 13.000s 82.008us 50 50 100.00
V2S sec_cm_ctrl_sparse aes_fi 16.000s 366.271us 50 50 100.00
aes_control_fi 49.000s 10.008ms 278 300 92.67
aes_cipher_fi 51.000s 10.008ms 333 350 95.14
aes_ctr_fi 13.000s 82.008us 50 50 100.00
V2S sec_cm_main_fsm_global_esc aes_alert_reset 1.050m 2.264ms 50 50 100.00
V2S sec_cm_main_fsm_local_esc aes_fi 16.000s 366.271us 50 50 100.00
aes_control_fi 49.000s 10.008ms 278 300 92.67
aes_cipher_fi 51.000s 10.008ms 333 350 95.14
aes_ctr_fi 13.000s 82.008us 50 50 100.00
V2S sec_cm_cipher_fsm_local_esc aes_fi 16.000s 366.271us 50 50 100.00
aes_control_fi 49.000s 10.008ms 278 300 92.67
aes_cipher_fi 51.000s 10.008ms 333 350 95.14
aes_ctr_fi 13.000s 82.008us 50 50 100.00
V2S sec_cm_ctr_fsm_local_esc aes_fi 16.000s 366.271us 50 50 100.00
aes_control_fi 49.000s 10.008ms 278 300 92.67
aes_ctr_fi 13.000s 82.008us 50 50 100.00
V2S sec_cm_data_reg_local_esc aes_fi 16.000s 366.271us 50 50 100.00
aes_control_fi 49.000s 10.008ms 278 300 92.67
aes_cipher_fi 51.000s 10.008ms 333 350 95.14
V2S TOTAL 944 985 95.84
V3 stress_all_with_rand_reset aes_stress_all_with_rand_reset 36.000s 1.049ms 0 10 0.00
V3 TOTAL 0 10 0.00
TOTAL 1551 1602 96.82

Testplan Progress

Items Total Written Passing Progress
V1 7 7 7 100.00
V2 13 13 13 100.00
V2S 11 11 7 63.64
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
98.40 98.60 96.44 99.45 95.91 97.72 100.00 98.96 96.61

Failure Buckets

Past Results