AES/MASKED Simulation Results

Sunday August 11 2024 23:02:21 UTC

GitHub Revision: `07b417ef03`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 6142445146730822936893044599112392910298048088673599708943858624824800218011

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	68.048us	1	1	100.00
V1	smoke	aes_smoke	24.000s	571.930us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	89.292us	5	5	100.00
V1	csr_rw	aes_csr_rw	9.000s	184.245us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	8.000s	606.063us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	87.357us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	7.000s	333.387us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	9.000s	184.245us	20	20	100.00
		aes_csr_aliasing	5.000s	87.357us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	24.000s	571.930us	50	50	100.00
		aes_config_error	19.000s	167.863us	50	50	100.00
		aes_stress	17.000s	485.764us	50	50	100.00
V2	key_length	aes_smoke	24.000s	571.930us	50	50	100.00
		aes_config_error	19.000s	167.863us	50	50	100.00
		aes_stress	17.000s	485.764us	50	50	100.00
V2	back2back	aes_stress	17.000s	485.764us	50	50	100.00
		aes_b2b	49.000s	610.218us	50	50	100.00
V2	backpressure	aes_stress	17.000s	485.764us	50	50	100.00
V2	multi_message	aes_smoke	24.000s	571.930us	50	50	100.00
		aes_config_error	19.000s	167.863us	50	50	100.00
		aes_stress	17.000s	485.764us	50	50	100.00
		aes_alert_reset	21.000s	4.101ms	50	50	100.00
V2	failure_test	aes_man_cfg_err	16.000s	65.071us	50	50	100.00
		aes_config_error	19.000s	167.863us	50	50	100.00
		aes_alert_reset	21.000s	4.101ms	50	50	100.00
V2	trigger_clear_test	aes_clear	1.200m	4.276ms	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	11.000s	331.937us	1	1	100.00
V2	reset_recovery	aes_alert_reset	21.000s	4.101ms	50	50	100.00
V2	stress	aes_stress	17.000s	485.764us	50	50	100.00
V2	sideload	aes_stress	17.000s	485.764us	50	50	100.00
		aes_sideload	26.000s	806.758us	50	50	100.00
V2	deinitialization	aes_deinit	28.000s	1.052ms	50	50	100.00
V2	stress_all	aes_stress_all	1.150m	1.005ms	10	10	100.00
V2	alert_test	aes_alert_test	13.000s	75.246us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	10.000s	872.933us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	10.000s	872.933us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	89.292us	5	5	100.00
		aes_csr_rw	9.000s	184.245us	20	20	100.00
		aes_csr_aliasing	5.000s	87.357us	5	5	100.00
		aes_same_csr_outstanding	9.000s	185.390us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	89.292us	5	5	100.00
		aes_csr_rw	9.000s	184.245us	20	20	100.00
		aes_csr_aliasing	5.000s	87.357us	5	5	100.00
		aes_same_csr_outstanding	9.000s	185.390us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	2.217m	4.192ms	50	50	100.00
V2S	fault_inject	aes_fi	56.000s	3.695ms	50	50	100.00
		aes_control_fi	51.000s	10.004ms	283	300	94.33
		aes_cipher_fi	26.000s	10.017ms	345	350	98.57
V2S	shadow_reg_update_error	aes_shadow_reg_errors	8.000s	85.511us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	8.000s	85.511us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	8.000s	85.511us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	8.000s	85.511us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	9.000s	144.911us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	10.000s	562.745us	5	5	100.00
		aes_tl_intg_err	10.000s	214.054us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	10.000s	214.054us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	21.000s	4.101ms	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	8.000s	85.511us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	24.000s	571.930us	50	50	100.00
		aes_stress	17.000s	485.764us	50	50	100.00
		aes_alert_reset	21.000s	4.101ms	50	50	100.00
		aes_core_fi	1.450m	10.003ms	67	70	95.71
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	8.000s	85.511us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	14.000s	121.238us	50	50	100.00
		aes_stress	17.000s	485.764us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	17.000s	485.764us	50	50	100.00
		aes_sideload	26.000s	806.758us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	14.000s	121.238us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	14.000s	121.238us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	14.000s	121.238us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	14.000s	121.238us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	14.000s	121.238us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	17.000s	485.764us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	17.000s	485.764us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	56.000s	3.695ms	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	56.000s	3.695ms	50	50	100.00
		aes_control_fi	51.000s	10.004ms	283	300	94.33
		aes_cipher_fi	26.000s	10.017ms	345	350	98.57
		aes_ctr_fi	9.000s	122.640us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	56.000s	3.695ms	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	56.000s	3.695ms	50	50	100.00
		aes_control_fi	51.000s	10.004ms	283	300	94.33
		aes_cipher_fi	26.000s	10.017ms	345	350	98.57
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	26.000s	10.017ms	345	350	98.57
V2S	sec_cm_ctr_fsm_sparse	aes_fi	56.000s	3.695ms	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	56.000s	3.695ms	50	50	100.00
		aes_control_fi	51.000s	10.004ms	283	300	94.33
		aes_ctr_fi	9.000s	122.640us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	56.000s	3.695ms	50	50	100.00
		aes_control_fi	51.000s	10.004ms	283	300	94.33
		aes_cipher_fi	26.000s	10.017ms	345	350	98.57
		aes_ctr_fi	9.000s	122.640us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	21.000s	4.101ms	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	56.000s	3.695ms	50	50	100.00
		aes_control_fi	51.000s	10.004ms	283	300	94.33
		aes_cipher_fi	26.000s	10.017ms	345	350	98.57
		aes_ctr_fi	9.000s	122.640us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	56.000s	3.695ms	50	50	100.00
		aes_control_fi	51.000s	10.004ms	283	300	94.33
		aes_cipher_fi	26.000s	10.017ms	345	350	98.57
		aes_ctr_fi	9.000s	122.640us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	56.000s	3.695ms	50	50	100.00
		aes_control_fi	51.000s	10.004ms	283	300	94.33
		aes_ctr_fi	9.000s	122.640us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	56.000s	3.695ms	50	50	100.00
		aes_control_fi	51.000s	10.004ms	283	300	94.33
		aes_cipher_fi	26.000s	10.017ms	345	350	98.57
V2S		TOTAL			960	985	97.46
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	2.933m	5.513ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1567	1602	97.82

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	13	100.00
V2S	11	11	8	72.73
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.33	98.52	96.25	99.41	95.76	97.72	97.78	98.96	97.41

Failure Buckets

Job aes_masked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 17 failures:
- Test aes_control_fi has 13 failures.
  - 16.aes_control_fi.96119463570421093366806101802169717957499162540112954613283520556956470411656
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/16.aes_control_fi/latest/run.log
```
  Job ID: smart:23616b90-4e81-43a0-abd7-e03b84afa142
```
  - 68.aes_control_fi.56293742717994030714446201708265716164152253795461083376356306776725353429795
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/68.aes_control_fi/latest/run.log
```
  Job ID: smart:40c23ad7-19a1-451c-82d2-cccfd1edfb35
```
  - ... and 11 more failures.
- Test aes_cipher_fi has 4 failures.
  - 49.aes_cipher_fi.761283818731103411035744253162654530843006057986447337792309746583155582807
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/49.aes_cipher_fi/latest/run.log
```
  Job ID: smart:f2e5d407-ca68-45a1-a608-6bbc3dfed194
```
  - 108.aes_cipher_fi.11916248907424446667805973940510894690144060752674108316826067380955328720148
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/108.aes_cipher_fi/latest/run.log
```
  Job ID: smart:55c99012-e3ca-4fca-a86c-276056ba074b
```
  - ... and 2 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 8 failures:

Test aes_stress_all_with_rand_reset has 8 failures.

1.aes_stress_all_with_rand_reset.66173288664010623992056768256483301815836564409595935796710051192077131500223
Line 1195, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2578456268 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 2578456268 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.aes_stress_all_with_rand_reset.63111747941165486392937729674961991106743597431450449744751116902684405295462
Line 1587, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2677738447 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 2677738447 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 4 failures:
- Test aes_control_fi has 4 failures.
  - 26.aes_control_fi.69555493127122322131789368978274640965954121749271838963565557157741843390258
    Line 317, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/26.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10009552776 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10009552776 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 42.aes_control_fi.81289054433109522562357153649291501600377224340556396380804593567561878237316
    Line 314, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/42.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10022409071 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10022409071 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 3 failures:
- Test aes_core_fi has 3 failures.
  - 53.aes_core_fi.98655533779826242973959562510131455498795307852920342820433833200017963221470
    Line 325, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/53.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10006362362 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006362362 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 60.aes_core_fi.95081075403006888718539989312010761718453459588361333136388089170102382144539
    Line 314, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/60.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10003104202 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10003104202 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 2 failures:

Test aes_stress_all_with_rand_reset has 2 failures.

0.aes_stress_all_with_rand_reset.7454370449197577153772365883617498234552668876863209267961503673267469037171
Line 922, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 3270486278 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 3270486278 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

7.aes_stress_all_with_rand_reset.115599169043346779248373784599595823507151651555206638628027105082828678015415
Line 1476, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/7.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 3033580560 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 3033580560 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_cipher_fi has 1 failures.
  - 208.aes_cipher_fi.92562294782748952167724953189390773017711246291079392816377717332462351205508
    Line 315, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/208.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10017080325 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10017080325 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```