AES/MASKED Simulation Results

Saturday August 17 2024 23:02:17 UTC

GitHub Revision: `76588857da`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 94235727392619910305578226901221990521512464990339520078429467885466612377995

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	4.000s	70.334us	1	1	100.00
V1	smoke	aes_smoke	17.000s	1.649ms	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	74.236us	5	5	100.00
V1	csr_rw	aes_csr_rw	8.000s	117.373us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	10.000s	859.726us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	4.000s	68.299us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	5.000s	58.539us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	8.000s	117.373us	20	20	100.00
		aes_csr_aliasing	4.000s	68.299us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	17.000s	1.649ms	50	50	100.00
		aes_config_error	18.000s	541.601us	50	50	100.00
		aes_stress	12.000s	201.745us	50	50	100.00
V2	key_length	aes_smoke	17.000s	1.649ms	50	50	100.00
		aes_config_error	18.000s	541.601us	50	50	100.00
		aes_stress	12.000s	201.745us	50	50	100.00
V2	back2back	aes_stress	12.000s	201.745us	50	50	100.00
		aes_b2b	42.000s	705.630us	50	50	100.00
V2	backpressure	aes_stress	12.000s	201.745us	50	50	100.00
V2	multi_message	aes_smoke	17.000s	1.649ms	50	50	100.00
		aes_config_error	18.000s	541.601us	50	50	100.00
		aes_stress	12.000s	201.745us	50	50	100.00
		aes_alert_reset	1.467m	2.604ms	50	50	100.00
V2	failure_test	aes_man_cfg_err	13.000s	60.586us	50	50	100.00
		aes_config_error	18.000s	541.601us	50	50	100.00
		aes_alert_reset	1.467m	2.604ms	50	50	100.00
V2	trigger_clear_test	aes_clear	19.000s	114.752us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	18.000s	1.006ms	1	1	100.00
V2	reset_recovery	aes_alert_reset	1.467m	2.604ms	50	50	100.00
V2	stress	aes_stress	12.000s	201.745us	50	50	100.00
V2	sideload	aes_stress	12.000s	201.745us	50	50	100.00
		aes_sideload	18.000s	604.506us	50	50	100.00
V2	deinitialization	aes_deinit	31.000s	844.686us	50	50	100.00
V2	stress_all	aes_stress_all	4.000m	7.593ms	10	10	100.00
V2	alert_test	aes_alert_test	9.000s	140.183us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	8.000s	67.291us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	8.000s	67.291us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	74.236us	5	5	100.00
		aes_csr_rw	8.000s	117.373us	20	20	100.00
		aes_csr_aliasing	4.000s	68.299us	5	5	100.00
		aes_same_csr_outstanding	5.000s	76.322us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	74.236us	5	5	100.00
		aes_csr_rw	8.000s	117.373us	20	20	100.00
		aes_csr_aliasing	4.000s	68.299us	5	5	100.00
		aes_same_csr_outstanding	5.000s	76.322us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	42.000s	5.796ms	50	50	100.00
V2S	fault_inject	aes_fi	41.000s	1.772ms	50	50	100.00
		aes_control_fi	30.000s	10.011ms	283	300	94.33
		aes_cipher_fi	49.000s	10.007ms	334	350	95.43
V2S	shadow_reg_update_error	aes_shadow_reg_errors	5.000s	91.339us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	5.000s	91.339us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	5.000s	91.339us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	5.000s	91.339us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	6.000s	116.282us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	18.000s	1.771ms	5	5	100.00
		aes_tl_intg_err	13.000s	176.428us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	13.000s	176.428us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	1.467m	2.604ms	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	5.000s	91.339us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	17.000s	1.649ms	50	50	100.00
		aes_stress	12.000s	201.745us	50	50	100.00
		aes_alert_reset	1.467m	2.604ms	50	50	100.00
		aes_core_fi	1.500m	10.027ms	64	70	91.43
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	5.000s	91.339us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	12.000s	151.620us	50	50	100.00
		aes_stress	12.000s	201.745us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	12.000s	201.745us	50	50	100.00
		aes_sideload	18.000s	604.506us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	12.000s	151.620us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	12.000s	151.620us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	12.000s	151.620us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	12.000s	151.620us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	12.000s	151.620us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	12.000s	201.745us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	12.000s	201.745us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	41.000s	1.772ms	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	41.000s	1.772ms	50	50	100.00
		aes_control_fi	30.000s	10.011ms	283	300	94.33
		aes_cipher_fi	49.000s	10.007ms	334	350	95.43
		aes_ctr_fi	13.000s	62.820us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	41.000s	1.772ms	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	41.000s	1.772ms	50	50	100.00
		aes_control_fi	30.000s	10.011ms	283	300	94.33
		aes_cipher_fi	49.000s	10.007ms	334	350	95.43
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	49.000s	10.007ms	334	350	95.43
V2S	sec_cm_ctr_fsm_sparse	aes_fi	41.000s	1.772ms	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	41.000s	1.772ms	50	50	100.00
		aes_control_fi	30.000s	10.011ms	283	300	94.33
		aes_ctr_fi	13.000s	62.820us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	41.000s	1.772ms	50	50	100.00
		aes_control_fi	30.000s	10.011ms	283	300	94.33
		aes_cipher_fi	49.000s	10.007ms	334	350	95.43
		aes_ctr_fi	13.000s	62.820us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	1.467m	2.604ms	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	41.000s	1.772ms	50	50	100.00
		aes_control_fi	30.000s	10.011ms	283	300	94.33
		aes_cipher_fi	49.000s	10.007ms	334	350	95.43
		aes_ctr_fi	13.000s	62.820us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	41.000s	1.772ms	50	50	100.00
		aes_control_fi	30.000s	10.011ms	283	300	94.33
		aes_cipher_fi	49.000s	10.007ms	334	350	95.43
		aes_ctr_fi	13.000s	62.820us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	41.000s	1.772ms	50	50	100.00
		aes_control_fi	30.000s	10.011ms	283	300	94.33
		aes_ctr_fi	13.000s	62.820us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	41.000s	1.772ms	50	50	100.00
		aes_control_fi	30.000s	10.011ms	283	300	94.33
		aes_cipher_fi	49.000s	10.007ms	334	350	95.43
V2S		TOTAL			946	985	96.04
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	1.050m	925.532us	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1553	1602	96.94

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	13	100.00
V2S	11	11	8	72.73
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.34	98.54	96.28	99.43	95.76	97.72	97.78	98.96	96.61

Failure Buckets

Job aes_masked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 20 failures:
- Test aes_control_fi has 15 failures.
  - 9.aes_control_fi.113631984151958984128445376315574474074574797583303211666681264632864526624866
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/9.aes_control_fi/latest/run.log
```
  Job ID: smart:bb365c28-2979-4042-95df-13ca05fc0575
```
  - 19.aes_control_fi.73470219407036867313727323032134838188728562675097951581014962547021944842541
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/19.aes_control_fi/latest/run.log
```
  Job ID: smart:81c3a396-4bf9-436a-a68f-693c8ca2196a
```
  - ... and 13 more failures.
- Test aes_cipher_fi has 5 failures.
  - 122.aes_cipher_fi.69715890993742508211284501961281978073805553432689260399858345723500122703869
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/122.aes_cipher_fi/latest/run.log
```
  Job ID: smart:8e90ac5c-a52a-40ef-b682-1b30c9d77ba0
```
  - 154.aes_cipher_fi.85990439055938487303797213313762288333859870141083845723610379334388583856476
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/154.aes_cipher_fi/latest/run.log
```
  Job ID: smart:7d467513-6d98-4e84-a125-874feedb0947
```
  - ... and 3 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 11 failures:
- Test aes_cipher_fi has 11 failures.
  - 11.aes_cipher_fi.33730725276832794866377808804847073874933387042671535101603641017217033220622
    Line 318, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/11.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10009102339 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10009102339 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 19.aes_cipher_fi.40312167004944054196370280330533451699795520804815830622011131394433390424651
    Line 319, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/19.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10022352717 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10022352717 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 9 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 8 failures:

Test aes_stress_all_with_rand_reset has 8 failures.

0.aes_stress_all_with_rand_reset.49661350738687363230886037728589427067297387876672941471644035559297620795414
Line 438, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @  69925339 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @  69925339 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.aes_stress_all_with_rand_reset.63296220174494357415152170368760582218080705309884485010804421846545836910725
Line 463, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 158609210 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 158609210 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 6 failures:
- Test aes_core_fi has 6 failures.
  - 1.aes_core_fi.59455590229300854336399257395189863639151051307406020734810531311043332703563
    Line 318, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10036214545 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10036214545 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 15.aes_core_fi.77160032366091317365013702047977129829547710466819229397601781238176044007924
    Line 327, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/15.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10008789913 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10008789913 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_control_fi has 2 failures.
  - 232.aes_control_fi.86278856988747702369133813441275345636986557347202911791552876308212829653138
    Line 322, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/232.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10011488885 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10011488885 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 270.aes_control_fi.112718041153624531176415389194738770601226193034037169518909947036173051170328
    Line 314, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/270.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10047190145 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10047190145 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:868) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 1.aes_stress_all_with_rand_reset.70061121758925689113869722877194714439712428776361547457485695442347969942710
    Line 505, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 405950491 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 405950491 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_stress_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 4.aes_stress_all_with_rand_reset.32962547312605508890540405669517381182307039583455583765233811156569703622574
    Line 344, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/4.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 147435603 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_stress_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 147435603 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```