AES/MASKED Simulation Results

Sunday August 18 2024 23:02:23 UTC

GitHub Revision: `f1535c5540`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 29514139809134543525249635699831421949407409612590789671953066019961489233719

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	4.000s	447.666us	1	1	100.00
V1	smoke	aes_smoke	11.000s	420.334us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	169.889us	5	5	100.00
V1	csr_rw	aes_csr_rw	3.000s	56.143us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	8.000s	423.393us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	6.000s	2.257ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	4.000s	93.248us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	3.000s	56.143us	20	20	100.00
		aes_csr_aliasing	6.000s	2.257ms	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	11.000s	420.334us	50	50	100.00
		aes_config_error	50.000s	1.805ms	50	50	100.00
		aes_stress	57.000s	1.858ms	50	50	100.00
V2	key_length	aes_smoke	11.000s	420.334us	50	50	100.00
		aes_config_error	50.000s	1.805ms	50	50	100.00
		aes_stress	57.000s	1.858ms	50	50	100.00
V2	back2back	aes_stress	57.000s	1.858ms	50	50	100.00
		aes_b2b	42.000s	488.687us	50	50	100.00
V2	backpressure	aes_stress	57.000s	1.858ms	50	50	100.00
V2	multi_message	aes_smoke	11.000s	420.334us	50	50	100.00
		aes_config_error	50.000s	1.805ms	50	50	100.00
		aes_stress	57.000s	1.858ms	50	50	100.00
		aes_alert_reset	9.000s	268.184us	49	50	98.00
V2	failure_test	aes_man_cfg_err	9.000s	56.770us	50	50	100.00
		aes_config_error	50.000s	1.805ms	50	50	100.00
		aes_alert_reset	9.000s	268.184us	49	50	98.00
V2	trigger_clear_test	aes_clear	18.000s	628.495us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	9.000s	495.532us	1	1	100.00
V2	reset_recovery	aes_alert_reset	9.000s	268.184us	49	50	98.00
V2	stress	aes_stress	57.000s	1.858ms	50	50	100.00
V2	sideload	aes_stress	57.000s	1.858ms	50	50	100.00
		aes_sideload	9.000s	425.119us	50	50	100.00
V2	deinitialization	aes_deinit	13.000s	362.399us	50	50	100.00
V2	stress_all	aes_stress_all	2.583m	5.286ms	10	10	100.00
V2	alert_test	aes_alert_test	8.000s	62.801us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	6.000s	642.311us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	6.000s	642.311us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	169.889us	5	5	100.00
		aes_csr_rw	3.000s	56.143us	20	20	100.00
		aes_csr_aliasing	6.000s	2.257ms	5	5	100.00
		aes_same_csr_outstanding	4.000s	111.841us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	169.889us	5	5	100.00
		aes_csr_rw	3.000s	56.143us	20	20	100.00
		aes_csr_aliasing	6.000s	2.257ms	5	5	100.00
		aes_same_csr_outstanding	4.000s	111.841us	20	20	100.00
V2		TOTAL			500	501	99.80
V2S	reseeding	aes_reseed	46.000s	4.125ms	50	50	100.00
V2S	fault_inject	aes_fi	54.000s	3.977ms	50	50	100.00
		aes_control_fi	30.000s	10.016ms	278	300	92.67
		aes_cipher_fi	48.000s	10.011ms	337	350	96.29
V2S	shadow_reg_update_error	aes_shadow_reg_errors	3.000s	87.022us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	3.000s	87.022us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	3.000s	87.022us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	3.000s	87.022us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	4.000s	70.899us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	11.000s	832.913us	5	5	100.00
		aes_tl_intg_err	6.000s	1.005ms	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	6.000s	1.005ms	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	9.000s	268.184us	49	50	98.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	3.000s	87.022us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	11.000s	420.334us	50	50	100.00
		aes_stress	57.000s	1.858ms	50	50	100.00
		aes_alert_reset	9.000s	268.184us	49	50	98.00
		aes_core_fi	57.000s	10.188ms	66	70	94.29
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	3.000s	87.022us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	8.000s	103.146us	50	50	100.00
		aes_stress	57.000s	1.858ms	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	57.000s	1.858ms	50	50	100.00
		aes_sideload	9.000s	425.119us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	8.000s	103.146us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	8.000s	103.146us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	8.000s	103.146us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	8.000s	103.146us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	8.000s	103.146us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	57.000s	1.858ms	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	57.000s	1.858ms	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	54.000s	3.977ms	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	54.000s	3.977ms	50	50	100.00
		aes_control_fi	30.000s	10.016ms	278	300	92.67
		aes_cipher_fi	48.000s	10.011ms	337	350	96.29
		aes_ctr_fi	14.000s	55.489us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	54.000s	3.977ms	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	54.000s	3.977ms	50	50	100.00
		aes_control_fi	30.000s	10.016ms	278	300	92.67
		aes_cipher_fi	48.000s	10.011ms	337	350	96.29
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	48.000s	10.011ms	337	350	96.29
V2S	sec_cm_ctr_fsm_sparse	aes_fi	54.000s	3.977ms	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	54.000s	3.977ms	50	50	100.00
		aes_control_fi	30.000s	10.016ms	278	300	92.67
		aes_ctr_fi	14.000s	55.489us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	54.000s	3.977ms	50	50	100.00
		aes_control_fi	30.000s	10.016ms	278	300	92.67
		aes_cipher_fi	48.000s	10.011ms	337	350	96.29
		aes_ctr_fi	14.000s	55.489us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	9.000s	268.184us	49	50	98.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	54.000s	3.977ms	50	50	100.00
		aes_control_fi	30.000s	10.016ms	278	300	92.67
		aes_cipher_fi	48.000s	10.011ms	337	350	96.29
		aes_ctr_fi	14.000s	55.489us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	54.000s	3.977ms	50	50	100.00
		aes_control_fi	30.000s	10.016ms	278	300	92.67
		aes_cipher_fi	48.000s	10.011ms	337	350	96.29
		aes_ctr_fi	14.000s	55.489us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	54.000s	3.977ms	50	50	100.00
		aes_control_fi	30.000s	10.016ms	278	300	92.67
		aes_ctr_fi	14.000s	55.489us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	54.000s	3.977ms	50	50	100.00
		aes_control_fi	30.000s	10.016ms	278	300	92.67
		aes_cipher_fi	48.000s	10.011ms	337	350	96.29
V2S		TOTAL			946	985	96.04
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	34.000s	1.464ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1552	1602	96.88

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	12	92.31
V2S	11	11	8	72.73
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.35	98.54	96.30	99.42	95.85	97.64	97.78	98.96	96.81

Failure Buckets

Job aes_masked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 29 failures:
- Test aes_control_fi has 19 failures.
  - 6.aes_control_fi.83723571149788309031382846048844882885386165701324729557282820115057954549201
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/6.aes_control_fi/latest/run.log
```
  Job ID: smart:effc8812-1adc-4568-ac0d-9aac76f4225f
```
  - 22.aes_control_fi.7835028309330362626919868667690364750854286579440475359227396271577542926761
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/22.aes_control_fi/latest/run.log
```
  Job ID: smart:50554daa-94c2-4b5c-95e6-397b923bbfd2
```
  - ... and 17 more failures.
- Test aes_cipher_fi has 10 failures.
  - 45.aes_cipher_fi.11329741670243322861273705938937477916464982862040053065707768959632672009949
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/45.aes_cipher_fi/latest/run.log
```
  Job ID: smart:94b52058-27ed-49cb-801d-c969a590b6ce
```
  - 78.aes_cipher_fi.26642308916874513253274896796875391876461881520062124541233105367467281417109
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/78.aes_cipher_fi/latest/run.log
```
  Job ID: smart:1113c230-a1d1-456d-ac3d-a70f5271c961
```
  - ... and 8 more failures.
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 4 failures:
- Test aes_core_fi has 4 failures.
  - 1.aes_core_fi.68233845694043199175861138253840290171255133037104561747723260622934127982479
    Line 315, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10009775506 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10009775506 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.aes_core_fi.1173043348950409378754981034609641011839635614229842727624907720710935172238
    Line 317, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/4.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10187758332 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10187758332 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
UVM_FATAL (aes_base_vseq.sv:74) [aes_reseed_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 3 failures:
- Test aes_stress_all_with_rand_reset has 3 failures.
  - 0.aes_stress_all_with_rand_reset.63407128711808722732723518359317219128497432975390917676491830095453411749818
    Line 348, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  61850997 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @  61850997 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 5.aes_stress_all_with_rand_reset.24143462596168229654196634778942930682985654156875182183504278620019572233636
    Line 330, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/5.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  76462256 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @  76462256 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 3 failures:

Test aes_stress_all_with_rand_reset has 3 failures.

2.aes_stress_all_with_rand_reset.98381575482661925412372092822167998631368425399631754572166313007386964079559
Line 973, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1639261674 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1639261674 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.aes_stress_all_with_rand_reset.35618509263049624033490400536410084679186619214456457751494847289128905452318
Line 934, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2409473503 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 2409473503 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 3 failures:
- Test aes_control_fi has 3 failures.
  - 24.aes_control_fi.87924189529182738689327196098026011331578143368531019847840199836995498516801
    Line 312, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/24.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10013016499 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10013016499 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 106.aes_control_fi.37731283258276378840656836919129093466179630601672584857462186134733958806880
    Line 329, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/106.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10015534860 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10015534860 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 3 failures:
- Test aes_cipher_fi has 3 failures.
  - 137.aes_cipher_fi.101178345367504816827049812753437465580739378739667395215985113984361023016078
    Line 324, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/137.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10025768374 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10025768374 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 304.aes_cipher_fi.44861846229982684101626846483670412519039665359305368026227947181044882475995
    Line 320, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/304.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10010666835 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10010666835 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL (aes_base_vseq.sv:74) [aes_stress_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 1.aes_stress_all_with_rand_reset.101251788273995041088231841820108772024444083049359611774167344919853352508125
    Line 330, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  95043040 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_stress_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @  95043040 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 4.aes_stress_all_with_rand_reset.80037969090430320230470998040905556282108795308856182613627711217720794390078
    Line 842, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/4.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 712128447 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 712128447 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:868) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 8.aes_stress_all_with_rand_reset.39767169318862515647526495023520250820226956429216836535635062368583621865976
    Line 375, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/8.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 792329664 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 792329664 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:868) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 9.aes_stress_all_with_rand_reset.108522916588459176891724278938452312479813181067677792342226108435856950118705
    Line 497, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/9.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 684431893 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 684431893 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,987): Assertion AesSecCmDataRegLocalEscDataOut has failed (* cycles, starting * PS) has 1 failures:
- Test aes_alert_reset has 1 failures.
  - 13.aes_alert_reset.86134590692480224898434829031190252715507670530356887686150540214282381501779
    Line 3519, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/13.aes_alert_reset/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,987): (time 43028465 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 42975833 PS)
  UVM_ERROR @  43028465 ps: (aes_core.sv:987) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut
  UVM_INFO @  43028465 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```