AES/MASKED Simulation Results

Monday August 19 2024 23:02:17 UTC

GitHub Revision: `e45ccd274a`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 28901767565311589526059483176077826609560752276120463932311122284088110669824

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	113.505us	1	1	100.00
V1	smoke	aes_smoke	13.000s	366.006us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	4.000s	143.920us	5	5	100.00
V1	csr_rw	aes_csr_rw	3.000s	54.388us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	8.000s	611.639us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	175.113us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	4.000s	110.278us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	3.000s	54.388us	20	20	100.00
		aes_csr_aliasing	5.000s	175.113us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	13.000s	366.006us	50	50	100.00
		aes_config_error	40.000s	1.241ms	50	50	100.00
		aes_stress	24.000s	1.430ms	50	50	100.00
V2	key_length	aes_smoke	13.000s	366.006us	50	50	100.00
		aes_config_error	40.000s	1.241ms	50	50	100.00
		aes_stress	24.000s	1.430ms	50	50	100.00
V2	back2back	aes_stress	24.000s	1.430ms	50	50	100.00
		aes_b2b	37.000s	396.731us	50	50	100.00
V2	backpressure	aes_stress	24.000s	1.430ms	50	50	100.00
V2	multi_message	aes_smoke	13.000s	366.006us	50	50	100.00
		aes_config_error	40.000s	1.241ms	50	50	100.00
		aes_stress	24.000s	1.430ms	50	50	100.00
		aes_alert_reset	1.117m	2.500ms	50	50	100.00
V2	failure_test	aes_man_cfg_err	11.000s	1.873ms	50	50	100.00
		aes_config_error	40.000s	1.241ms	50	50	100.00
		aes_alert_reset	1.117m	2.500ms	50	50	100.00
V2	trigger_clear_test	aes_clear	15.000s	296.058us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	11.000s	3.409ms	1	1	100.00
V2	reset_recovery	aes_alert_reset	1.117m	2.500ms	50	50	100.00
V2	stress	aes_stress	24.000s	1.430ms	50	50	100.00
V2	sideload	aes_stress	24.000s	1.430ms	50	50	100.00
		aes_sideload	44.000s	1.497ms	50	50	100.00
V2	deinitialization	aes_deinit	55.000s	3.332ms	50	50	100.00
V2	stress_all	aes_stress_all	1.150m	3.059ms	10	10	100.00
V2	alert_test	aes_alert_test	8.000s	67.508us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	5.000s	221.427us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	5.000s	221.427us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	4.000s	143.920us	5	5	100.00
		aes_csr_rw	3.000s	54.388us	20	20	100.00
		aes_csr_aliasing	5.000s	175.113us	5	5	100.00
		aes_same_csr_outstanding	5.000s	68.259us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	4.000s	143.920us	5	5	100.00
		aes_csr_rw	3.000s	54.388us	20	20	100.00
		aes_csr_aliasing	5.000s	175.113us	5	5	100.00
		aes_same_csr_outstanding	5.000s	68.259us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	23.000s	1.504ms	50	50	100.00
V2S	fault_inject	aes_fi	22.000s	739.428us	50	50	100.00
		aes_control_fi	40.000s	10.130ms	274	300	91.33
		aes_cipher_fi	50.000s	10.095ms	337	350	96.29
V2S	shadow_reg_update_error	aes_shadow_reg_errors	4.000s	113.974us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	4.000s	113.974us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	4.000s	113.974us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	4.000s	113.974us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	4.000s	81.266us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	8.000s	789.710us	5	5	100.00
		aes_tl_intg_err	5.000s	116.110us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	5.000s	116.110us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	1.117m	2.500ms	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	4.000s	113.974us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	13.000s	366.006us	50	50	100.00
		aes_stress	24.000s	1.430ms	50	50	100.00
		aes_alert_reset	1.117m	2.500ms	50	50	100.00
		aes_core_fi	32.000s	10.157ms	68	70	97.14
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	4.000s	113.974us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	4.000s	75.350us	50	50	100.00
		aes_stress	24.000s	1.430ms	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	24.000s	1.430ms	50	50	100.00
		aes_sideload	44.000s	1.497ms	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	4.000s	75.350us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	4.000s	75.350us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	4.000s	75.350us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	4.000s	75.350us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	4.000s	75.350us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	24.000s	1.430ms	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	24.000s	1.430ms	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	22.000s	739.428us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	22.000s	739.428us	50	50	100.00
		aes_control_fi	40.000s	10.130ms	274	300	91.33
		aes_cipher_fi	50.000s	10.095ms	337	350	96.29
		aes_ctr_fi	5.000s	221.207us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	22.000s	739.428us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	22.000s	739.428us	50	50	100.00
		aes_control_fi	40.000s	10.130ms	274	300	91.33
		aes_cipher_fi	50.000s	10.095ms	337	350	96.29
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	50.000s	10.095ms	337	350	96.29
V2S	sec_cm_ctr_fsm_sparse	aes_fi	22.000s	739.428us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	22.000s	739.428us	50	50	100.00
		aes_control_fi	40.000s	10.130ms	274	300	91.33
		aes_ctr_fi	5.000s	221.207us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	22.000s	739.428us	50	50	100.00
		aes_control_fi	40.000s	10.130ms	274	300	91.33
		aes_cipher_fi	50.000s	10.095ms	337	350	96.29
		aes_ctr_fi	5.000s	221.207us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	1.117m	2.500ms	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	22.000s	739.428us	50	50	100.00
		aes_control_fi	40.000s	10.130ms	274	300	91.33
		aes_cipher_fi	50.000s	10.095ms	337	350	96.29
		aes_ctr_fi	5.000s	221.207us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	22.000s	739.428us	50	50	100.00
		aes_control_fi	40.000s	10.130ms	274	300	91.33
		aes_cipher_fi	50.000s	10.095ms	337	350	96.29
		aes_ctr_fi	5.000s	221.207us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	22.000s	739.428us	50	50	100.00
		aes_control_fi	40.000s	10.130ms	274	300	91.33
		aes_ctr_fi	5.000s	221.207us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	22.000s	739.428us	50	50	100.00
		aes_control_fi	40.000s	10.130ms	274	300	91.33
		aes_cipher_fi	50.000s	10.095ms	337	350	96.29
V2S		TOTAL			944	985	95.84
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	52.000s	4.706ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1551	1602	96.82

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	13	100.00
V2S	11	11	8	72.73
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.30	98.51	96.21	99.38	95.63	97.72	97.78	98.96	97.60

Failure Buckets

Job aes_masked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 21 failures:
- Test aes_control_fi has 17 failures.
  - 23.aes_control_fi.18291572939384262104313316159503715787557054580086721765421195382670753654470
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/23.aes_control_fi/latest/run.log
```
  Job ID: smart:2c91e003-d8c3-4e05-92dc-a99a34cc87d1
```
  - 58.aes_control_fi.58081474675605900548403844646869516872575900970775542675276128034571668560374
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/58.aes_control_fi/latest/run.log
```
  Job ID: smart:205ca212-b835-49e7-bb68-60d03010a513
```
  - ... and 15 more failures.
- Test aes_cipher_fi has 4 failures.
  - 36.aes_cipher_fi.114538402924192773941210584248590785123241689703620917520223380128210187446512
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/36.aes_cipher_fi/latest/run.log
```
  Job ID: smart:bb7e688f-d2ac-4130-94f6-f45f5fdf1c1e
```
  - 59.aes_cipher_fi.63818659009586045084899115590047443340520359485971243262380119101368843548488
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/59.aes_cipher_fi/latest/run.log
```
  Job ID: smart:9a36002e-3e70-4324-a3d7-53c4a8070862
```
  - ... and 2 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 9 failures:
- Test aes_control_fi has 9 failures.
  - 10.aes_control_fi.80357584892607106967436890793620807395006326685803299369352675838200976188265
    Line 325, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/10.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10130339576 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10130339576 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 46.aes_control_fi.84285109092247523721119454609291114285822746645874066368942171157006686679171
    Line 323, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/46.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10008199659 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10008199659 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 7 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 9 failures:
- Test aes_cipher_fi has 9 failures.
  - 33.aes_cipher_fi.28555432715219861788093961922065524805938764963852004277333858360772226133886
    Line 327, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/33.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10004551686 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10004551686 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 149.aes_cipher_fi.24774947778114012117686384241373832286138151062344017207264494565897808226151
    Line 321, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/149.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10027047614 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10027047614 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 7 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 7 failures:

Test aes_stress_all_with_rand_reset has 7 failures.

0.aes_stress_all_with_rand_reset.62449718645935802359248388140042724489115308830473122151963197487747670842072
Line 655, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 365257793 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 365257793 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.aes_stress_all_with_rand_reset.15313673632127915954317241407797152613955439484485557987959178168127103256998
Line 1422, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 4706470846 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 4706470846 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_core_fi has 2 failures.
  - 2.aes_core_fi.86262881823782814879246250807586275147166223085300829200100689175477285345839
    Line 324, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/2.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10157361642 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10157361642 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 27.aes_core_fi.115000908359361653815076485987752403532933198208038452856098215888617342034367
    Line 331, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/27.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10028573852 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10028573852 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_reseed_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 1.aes_stress_all_with_rand_reset.99180488212866871495480835953125535739407910013600862241598035333343422947568
    Line 328, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  90740300 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @  90740300 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 3.aes_stress_all_with_rand_reset.2921072394167060367410196735247358157833951234876209607835197374031812965529
    Line 675, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1178203597 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1178203597 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_stress_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 7.aes_stress_all_with_rand_reset.107537654838891197985767071461523894596626210937872668322567669179934904118732
    Line 544, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/7.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 394230427 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_stress_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 394230427 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```