AES/MASKED Simulation Results

Wednesday August 21 2024 01:12:47 UTC

GitHub Revision: `34b8fc33e3`

Branch: earlgrey_1_0_0_2024_08_20_RC0

Simulator: XCELIUM

Build randomization enabled with --build-seed 77645589415139663032322841827996135987237190720163469870959218015679941996572

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	4.000s	113.613us	1	1	100.00
V1	smoke	aes_smoke	1.417m	81.694us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	42.000s	76.724us	5	5	100.00
V1	csr_rw	aes_csr_rw	32.000s	79.244us	19	20	95.00
V1	csr_bit_bash	aes_csr_bit_bash	1.033m	620.995us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	50.000s	75.571us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	32.000s	90.462us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	32.000s	79.244us	19	20	95.00
		aes_csr_aliasing	50.000s	75.571us	5	5	100.00
V1		TOTAL			105	106	99.06
V2	algorithm	aes_smoke	1.417m	81.694us	50	50	100.00
		aes_config_error	1.433m	117.515us	50	50	100.00
		aes_stress	1.450m	70.085us	50	50	100.00
V2	key_length	aes_smoke	1.417m	81.694us	50	50	100.00
		aes_config_error	1.433m	117.515us	50	50	100.00
		aes_stress	1.450m	70.085us	50	50	100.00
V2	back2back	aes_stress	1.450m	70.085us	50	50	100.00
		aes_b2b	1.517m	204.172us	50	50	100.00
V2	backpressure	aes_stress	1.450m	70.085us	50	50	100.00
V2	multi_message	aes_smoke	1.417m	81.694us	50	50	100.00
		aes_config_error	1.433m	117.515us	50	50	100.00
		aes_stress	1.450m	70.085us	50	50	100.00
		aes_alert_reset	1.467m	191.385us	50	50	100.00
V2	failure_test	aes_man_cfg_err	1.567m	76.309us	50	50	100.00
		aes_config_error	1.433m	117.515us	50	50	100.00
		aes_alert_reset	1.467m	191.385us	50	50	100.00
V2	trigger_clear_test	aes_clear	3.850m	5.294ms	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	12.000s	1.321ms	1	1	100.00
V2	reset_recovery	aes_alert_reset	1.467m	191.385us	50	50	100.00
V2	stress	aes_stress	1.450m	70.085us	50	50	100.00
V2	sideload	aes_stress	1.450m	70.085us	50	50	100.00
		aes_sideload	1.500m	76.062us	50	50	100.00
V2	deinitialization	aes_deinit	1.433m	104.878us	50	50	100.00
V2	stress_all	aes_stress_all	2.333m	5.027ms	10	10	100.00
V2	alert_test	aes_alert_test	1.567m	78.484us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	45.000s	146.478us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	45.000s	146.478us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	42.000s	76.724us	5	5	100.00
		aes_csr_rw	32.000s	79.244us	19	20	95.00
		aes_csr_aliasing	50.000s	75.571us	5	5	100.00
		aes_same_csr_outstanding	33.000s	64.971us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	42.000s	76.724us	5	5	100.00
		aes_csr_rw	32.000s	79.244us	19	20	95.00
		aes_csr_aliasing	50.000s	75.571us	5	5	100.00
		aes_same_csr_outstanding	33.000s	64.971us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	40.183m	37.573ms	50	50	100.00
V2S	fault_inject	aes_fi	1.433m	158.979us	50	50	100.00
		aes_control_fi	56.000s	10.061ms	228	300	76.00
		aes_cipher_fi	56.000s	59.836us	249	350	71.14
V2S	shadow_reg_update_error	aes_shadow_reg_errors	43.000s	59.224us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	43.000s	59.224us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	43.000s	59.224us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	43.000s	59.224us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	1.250m	154.021us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	1.450m	1.661ms	5	5	100.00
		aes_tl_intg_err	44.000s	113.058us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	44.000s	113.058us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	1.467m	191.385us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	43.000s	59.224us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	1.417m	81.694us	50	50	100.00
		aes_stress	1.450m	70.085us	50	50	100.00
		aes_alert_reset	1.467m	191.385us	50	50	100.00
		aes_core_fi	2.750m	10.016ms	67	70	95.71
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	43.000s	59.224us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	1.500m	60.562us	50	50	100.00
		aes_stress	1.450m	70.085us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	1.450m	70.085us	50	50	100.00
		aes_sideload	1.500m	76.062us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	1.500m	60.562us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	1.500m	60.562us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	1.500m	60.562us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	1.500m	60.562us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	1.500m	60.562us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	1.450m	70.085us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	1.450m	70.085us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	1.433m	158.979us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	1.433m	158.979us	50	50	100.00
		aes_control_fi	56.000s	10.061ms	228	300	76.00
		aes_cipher_fi	56.000s	59.836us	249	350	71.14
		aes_ctr_fi	17.000s	57.542us	38	50	76.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	1.433m	158.979us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	1.433m	158.979us	50	50	100.00
		aes_control_fi	56.000s	10.061ms	228	300	76.00
		aes_cipher_fi	56.000s	59.836us	249	350	71.14
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	56.000s	59.836us	249	350	71.14
V2S	sec_cm_ctr_fsm_sparse	aes_fi	1.433m	158.979us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	1.433m	158.979us	50	50	100.00
		aes_control_fi	56.000s	10.061ms	228	300	76.00
		aes_ctr_fi	17.000s	57.542us	38	50	76.00
V2S	sec_cm_ctrl_sparse	aes_fi	1.433m	158.979us	50	50	100.00
		aes_control_fi	56.000s	10.061ms	228	300	76.00
		aes_cipher_fi	56.000s	59.836us	249	350	71.14
		aes_ctr_fi	17.000s	57.542us	38	50	76.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	1.467m	191.385us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	1.433m	158.979us	50	50	100.00
		aes_control_fi	56.000s	10.061ms	228	300	76.00
		aes_cipher_fi	56.000s	59.836us	249	350	71.14
		aes_ctr_fi	17.000s	57.542us	38	50	76.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	1.433m	158.979us	50	50	100.00
		aes_control_fi	56.000s	10.061ms	228	300	76.00
		aes_cipher_fi	56.000s	59.836us	249	350	71.14
		aes_ctr_fi	17.000s	57.542us	38	50	76.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	1.433m	158.979us	50	50	100.00
		aes_control_fi	56.000s	10.061ms	228	300	76.00
		aes_ctr_fi	17.000s	57.542us	38	50	76.00
V2S	sec_cm_data_reg_local_esc	aes_fi	1.433m	158.979us	50	50	100.00
		aes_control_fi	56.000s	10.061ms	228	300	76.00
		aes_cipher_fi	56.000s	59.836us	249	350	71.14
V2S		TOTAL			797	985	80.91
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	2.117m	1.469ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1403	1602	87.58

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	6	85.71
V2	13	13	13	100.00
V2S	11	11	7	63.64
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.29	98.48	96.14	99.42	95.67	97.72	97.78	98.96	96.01

Failure Buckets

Job timed out after * minutes has 180 failures:
- Test aes_control_fi has 69 failures.
  - 5.aes_control_fi.78854671886749366261884534936348558582371436163801730254987454335278902226753
    Log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aes_masked-sim-xcelium/5.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 6.aes_control_fi.8693757617029616983704329003325457089782459372374765833491035680119500605039
    Log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aes_masked-sim-xcelium/6.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 67 more failures.
- Test aes_cipher_fi has 99 failures.
  - 5.aes_cipher_fi.13113624428912060549758273825425803364833760539184941086928789502410821247265
    Log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aes_masked-sim-xcelium/5.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 6.aes_cipher_fi.27505187788102848282073324079142701985709693222216265229140749557042525414837
    Log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aes_masked-sim-xcelium/6.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 97 more failures.
- Test aes_ctr_fi has 12 failures.
  - 5.aes_ctr_fi.91440681157275437090423815939776511748027562314033037869572565321203428770636
    Log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aes_masked-sim-xcelium/5.aes_ctr_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 6.aes_ctr_fi.5756277969160717661021554287996832144914328295043826054066950873961101316346
    Log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aes_masked-sim-xcelium/6.aes_ctr_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 10 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 5 failures:

Test aes_stress_all_with_rand_reset has 5 failures.

0.aes_stress_all_with_rand_reset.59775850726980438650117367528764897064254841779303905487476240062067274882015
Line 744, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 488780320 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 488780320 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.27146056222086545628883218219813299060472657224283279625865380434697716750094
Line 1030, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 3651000833 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 3651000833 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 3 failures:
- Test aes_control_fi has 3 failures.
  - 122.aes_control_fi.15173425548351794181648879061077925258417279386185378057369194814919478256575
    Line 140, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aes_masked-sim-xcelium/122.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10061467526 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10061467526 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 135.aes_control_fi.67647494638210514773529759163093921698908325710789168964489975338518258603461
    Line 129, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aes_masked-sim-xcelium/135.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10060152678 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10060152678 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL (aes_base_vseq.sv:74) [aes_reseed_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 2 failures:
- Test aes_stress_all_with_rand_reset has 2 failures.
  - 2.aes_stress_all_with_rand_reset.8617977194281114836836803210254461976812857252672041387515936032671844072207
    Line 156, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aes_masked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 192979200 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 192979200 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 6.aes_stress_all_with_rand_reset.27316129290544042302422271272658313979080137400832806141169764811171397987909
    Line 138, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aes_masked-sim-xcelium/6.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  15658092 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @  15658092 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_core_fi has 2 failures.
  - 45.aes_core_fi.89244572926806521384556383305545124266856633699360952991788634650025980368733
    Line 137, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aes_masked-sim-xcelium/45.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10015577272 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10015577272 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 49.aes_core_fi.69757342150114040866172563136479906086150702857759359797000703749368025106345
    Line 132, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aes_masked-sim-xcelium/49.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10063596932 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10063596932 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_cipher_fi has 2 failures.
  - 113.aes_cipher_fi.97727497690924480524711500549315338346057595724106798402507810233803841101914
    Line 131, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aes_masked-sim-xcelium/113.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10011582315 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10011582315 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 296.aes_cipher_fi.105357855239196058269760601797318923364117603288214813397836714155266017186693
    Line 138, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aes_masked-sim-xcelium/296.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10012998190 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10012998190 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_alert_reset_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 4.aes_stress_all_with_rand_reset.115581368706810514701519760516912904360658357267006488529409255665878587693705
    Line 132, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aes_masked-sim-xcelium/4.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 127602343 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 127602343 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:868) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 7.aes_stress_all_with_rand_reset.108458101524725101164970181248638400761641579510280559959307756080735312610869
    Line 153, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aes_masked-sim-xcelium/7.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 461080767 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 461080767 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_stress_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 9.aes_stress_all_with_rand_reset.7954907922450427400165586579002472583996677018013009582941925047081715443621
    Line 183, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aes_masked-sim-xcelium/9.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 186908423 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_stress_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 186908423 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

xmsim: *E,ASRTST (/workspaces/lowrisc/opentitan/scratch/earlgrey_*_*_*_*_*_*_RC0/aes_masked-sim-xcelium/cover_reg_top/src/lowrisc_ip_aes_*/rtl/aes_cipher_core.sv,876): Assertion AesSecCmKeyMaskingStateShare has failed (* cycles, starting * PS) has 1 failures:

Test aes_csr_rw has 1 failures.

13.aes_csr_rw.77781837984931361364429027327438861878207940739490743302929567384958230695973
Line 100, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aes_masked-sim-xcelium/13.aes_csr_rw/latest/run.log

  xmsim: *E,ASRTST (/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aes_masked-sim-xcelium/cover_reg_top/src/lowrisc_ip_aes_1.0/rtl/aes_cipher_core.sv,876): (time 6224433 PS) Assertion tb.dut.u_aes_core.u_aes_cipher_core.gen_sec_cm_key_masking_svas.gen_sec_cm_key_masking_share_svas[1].AesSecCmKeyMaskingStateShare has failed (2 cycles, starting 6204433 PS)
  UVM_ERROR @   6224433 ps: (aes_cipher_core.sv:876) [ASSERT FAILED] AesSecCmKeyMaskingStateShare
  UVM_INFO @   6224433 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=7) has 1 failures:
- Test aes_core_fi has 1 failures.
  - 14.aes_core_fi.73555197809525753762021336688520219289309355687433879404900507803197807152401
    Line 123, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aes_masked-sim-xcelium/14.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10016209067 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0x2e540084, Comparison=CompareOpEq, exp_data=0x0, call_count=7)
  UVM_INFO @ 10016209067 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```