AES/MASKED Simulation Results

Thursday August 22 2024 22:02:20 UTC

GitHub Revision: `0825c81be0`

Branch: os_regression_2024_08_22

Simulator: XCELIUM

Build randomization enabled with --build-seed 102736032995262985039236458937944411119924968439319752111682827040046827694889

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	5.000s	116.797us	1	1	100.00
V1	smoke	aes_smoke	27.000s	361.387us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	31.000s	84.792us	5	5	100.00
V1	csr_rw	aes_csr_rw	35.000s	58.676us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	36.000s	996.029us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	33.000s	91.797us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	30.000s	72.944us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	35.000s	58.676us	20	20	100.00
		aes_csr_aliasing	33.000s	91.797us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	27.000s	361.387us	50	50	100.00
		aes_config_error	28.000s	103.668us	50	50	100.00
		aes_stress	1.083m	2.537ms	50	50	100.00
V2	key_length	aes_smoke	27.000s	361.387us	50	50	100.00
		aes_config_error	28.000s	103.668us	50	50	100.00
		aes_stress	1.083m	2.537ms	50	50	100.00
V2	back2back	aes_stress	1.083m	2.537ms	50	50	100.00
		aes_b2b	41.000s	771.954us	50	50	100.00
V2	backpressure	aes_stress	1.083m	2.537ms	50	50	100.00
V2	multi_message	aes_smoke	27.000s	361.387us	50	50	100.00
		aes_config_error	28.000s	103.668us	50	50	100.00
		aes_stress	1.083m	2.537ms	50	50	100.00
		aes_alert_reset	30.000s	72.031us	50	50	100.00
V2	failure_test	aes_man_cfg_err	28.000s	112.459us	50	50	100.00
		aes_config_error	28.000s	103.668us	50	50	100.00
		aes_alert_reset	30.000s	72.031us	50	50	100.00
V2	trigger_clear_test	aes_clear	33.000s	1.517ms	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	15.000s	1.358ms	1	1	100.00
V2	reset_recovery	aes_alert_reset	30.000s	72.031us	50	50	100.00
V2	stress	aes_stress	1.083m	2.537ms	50	50	100.00
V2	sideload	aes_stress	1.083m	2.537ms	50	50	100.00
		aes_sideload	26.000s	197.646us	50	50	100.00
V2	deinitialization	aes_deinit	28.000s	113.016us	50	50	100.00
V2	stress_all	aes_stress_all	5.750m	13.150ms	10	10	100.00
V2	alert_test	aes_alert_test	26.000s	63.807us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	37.000s	103.169us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	37.000s	103.169us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	31.000s	84.792us	5	5	100.00
		aes_csr_rw	35.000s	58.676us	20	20	100.00
		aes_csr_aliasing	33.000s	91.797us	5	5	100.00
		aes_same_csr_outstanding	36.000s	94.365us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	31.000s	84.792us	5	5	100.00
		aes_csr_rw	35.000s	58.676us	20	20	100.00
		aes_csr_aliasing	33.000s	91.797us	5	5	100.00
		aes_same_csr_outstanding	36.000s	94.365us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	33.000s	1.167ms	50	50	100.00
V2S	fault_inject	aes_fi	28.000s	201.842us	48	50	96.00
		aes_control_fi	1.000m	10.014ms	277	300	92.33
		aes_cipher_fi	52.000s	75.101us	339	350	96.86
V2S	shadow_reg_update_error	aes_shadow_reg_errors	31.000s	159.192us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	31.000s	159.192us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	31.000s	159.192us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	31.000s	159.192us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	36.000s	90.959us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	16.000s	4.044ms	5	5	100.00
		aes_tl_intg_err	39.000s	143.939us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	39.000s	143.939us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	30.000s	72.031us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	31.000s	159.192us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	27.000s	361.387us	50	50	100.00
		aes_stress	1.083m	2.537ms	50	50	100.00
		aes_alert_reset	30.000s	72.031us	50	50	100.00
		aes_core_fi	1.267m	10.004ms	67	70	95.71
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	31.000s	159.192us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	26.000s	85.146us	50	50	100.00
		aes_stress	1.083m	2.537ms	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	1.083m	2.537ms	50	50	100.00
		aes_sideload	26.000s	197.646us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	26.000s	85.146us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	26.000s	85.146us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	26.000s	85.146us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	26.000s	85.146us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	26.000s	85.146us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	1.083m	2.537ms	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	1.083m	2.537ms	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	28.000s	201.842us	48	50	96.00
V2S	sec_cm_main_fsm_redun	aes_fi	28.000s	201.842us	48	50	96.00
		aes_control_fi	1.000m	10.014ms	277	300	92.33
		aes_cipher_fi	52.000s	75.101us	339	350	96.86
		aes_ctr_fi	52.000s	10.014ms	49	50	98.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	28.000s	201.842us	48	50	96.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	28.000s	201.842us	48	50	96.00
		aes_control_fi	1.000m	10.014ms	277	300	92.33
		aes_cipher_fi	52.000s	75.101us	339	350	96.86
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	52.000s	75.101us	339	350	96.86
V2S	sec_cm_ctr_fsm_sparse	aes_fi	28.000s	201.842us	48	50	96.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	28.000s	201.842us	48	50	96.00
		aes_control_fi	1.000m	10.014ms	277	300	92.33
		aes_ctr_fi	52.000s	10.014ms	49	50	98.00
V2S	sec_cm_ctrl_sparse	aes_fi	28.000s	201.842us	48	50	96.00
		aes_control_fi	1.000m	10.014ms	277	300	92.33
		aes_cipher_fi	52.000s	75.101us	339	350	96.86
		aes_ctr_fi	52.000s	10.014ms	49	50	98.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	30.000s	72.031us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	28.000s	201.842us	48	50	96.00
		aes_control_fi	1.000m	10.014ms	277	300	92.33
		aes_cipher_fi	52.000s	75.101us	339	350	96.86
		aes_ctr_fi	52.000s	10.014ms	49	50	98.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	28.000s	201.842us	48	50	96.00
		aes_control_fi	1.000m	10.014ms	277	300	92.33
		aes_cipher_fi	52.000s	75.101us	339	350	96.86
		aes_ctr_fi	52.000s	10.014ms	49	50	98.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	28.000s	201.842us	48	50	96.00
		aes_control_fi	1.000m	10.014ms	277	300	92.33
		aes_ctr_fi	52.000s	10.014ms	49	50	98.00
V2S	sec_cm_data_reg_local_esc	aes_fi	28.000s	201.842us	48	50	96.00
		aes_control_fi	1.000m	10.014ms	277	300	92.33
		aes_cipher_fi	52.000s	75.101us	339	350	96.86
V2S		TOTAL			945	985	95.94
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	38.000s	1.357ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1552	1602	96.88

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	13	100.00
V2S	11	11	6	54.55
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.33	98.53	96.25	99.43	95.72	97.72	98.52	98.96	96.81

Failure Buckets

Job timed out after * minutes has 20 failures:
- Test aes_control_fi has 15 failures.
  - 25.aes_control_fi.1142678862040688054022738603388745227950003838111276158719362089320108538382
    Log /workspaces/repo/scratch/os_regression_2024_08_22/aes_masked-sim-xcelium/25.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 42.aes_control_fi.1755839962387377403833087959351090894167961748124498472251949222350968996146
    Log /workspaces/repo/scratch/os_regression_2024_08_22/aes_masked-sim-xcelium/42.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 13 more failures.
- Test aes_cipher_fi has 5 failures.
  - 36.aes_cipher_fi.83945804846757159484998177626430556739743594778519572787769375932063926604429
    Log /workspaces/repo/scratch/os_regression_2024_08_22/aes_masked-sim-xcelium/36.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 165.aes_cipher_fi.55014102162594618498418355016949774033620451701977799026424815012789872391366
    Log /workspaces/repo/scratch/os_regression_2024_08_22/aes_masked-sim-xcelium/165.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 3 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 8 failures:

Test aes_stress_all_with_rand_reset has 8 failures.

0.aes_stress_all_with_rand_reset.104013358731231566872914991269968725124032921701853800558243317154652892690454
Line 175, in log /workspaces/repo/scratch/os_regression_2024_08_22/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @  70176811 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @  70176811 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.aes_stress_all_with_rand_reset.98636375462807868688175603718447420546935951176577965902849656151779709794817
Line 676, in log /workspaces/repo/scratch/os_regression_2024_08_22/aes_masked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 619481744 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 619481744 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 8 failures:
- Test aes_control_fi has 8 failures.
  - 50.aes_control_fi.82304417939229539240140702410801039559293707718271514252394065906995182172074
    Line 133, in log /workspaces/repo/scratch/os_regression_2024_08_22/aes_masked-sim-xcelium/50.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10008575797 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10008575797 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 66.aes_control_fi.40133192757288560788295804492421912453731267134900941596530543382686169803890
    Line 132, in log /workspaces/repo/scratch/os_regression_2024_08_22/aes_masked-sim-xcelium/66.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10140241466 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10140241466 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 6 failures:
- Test aes_cipher_fi has 6 failures.
  - 46.aes_cipher_fi.43778680155841134036369175413080378669650913841194982932298795452686713809671
    Line 134, in log /workspaces/repo/scratch/os_regression_2024_08_22/aes_masked-sim-xcelium/46.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10103502183 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10103502183 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 60.aes_cipher_fi.79404664457719132431308664302640896378482047603535966656849722119258277977017
    Line 131, in log /workspaces/repo/scratch/os_regression_2024_08_22/aes_masked-sim-xcelium/60.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10024391345 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10024391345 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 3 failures:
- Test aes_core_fi has 3 failures.
  - 12.aes_core_fi.47488269280706809069881511275662561811210363733511334608931652315643606650143
    Line 130, in log /workspaces/repo/scratch/os_regression_2024_08_22/aes_masked-sim-xcelium/12.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10004075616 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10004075616 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 31.aes_core_fi.50738774802695293250501966748339180064100073235327144544095783328669532496462
    Line 129, in log /workspaces/repo/scratch/os_regression_2024_08_22/aes_masked-sim-xcelium/31.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10003922328 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10003922328 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.

UVM_FATAL (aes_fi_vseq.sv:69) virtual_sequencer [aes_fi_vseq] Was Able to finish without clearing reset has 2 failures:

Test aes_fi has 2 failures.

6.aes_fi.95892825585591427205315227834773714729957237601373346768838578111585299883691
Line 24974, in log /workspaces/repo/scratch/os_regression_2024_08_22/aes_masked-sim-xcelium/6.aes_fi/latest/run.log

  UVM_FATAL @ 307478374 ps: (aes_fi_vseq.sv:69) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.aes_fi_vseq] Was Able to finish without clearing reset
  UVM_INFO @ 307478374 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

18.aes_fi.60495922058205634465200096774803994322679151230887400944108091174170300485595
Line 30892, in log /workspaces/repo/scratch/os_regression_2024_08_22/aes_masked-sim-xcelium/18.aes_fi/latest/run.log

  UVM_FATAL @  69727850 ps: (aes_fi_vseq.sv:69) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.aes_fi_vseq] Was Able to finish without clearing reset
  UVM_INFO @  69727850 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (aes_base_vseq.sv:74) [aes_stress_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 1.aes_stress_all_with_rand_reset.110606298700793909988906402682501860487861701837202692511323603896087644477594
    Line 151, in log /workspaces/repo/scratch/os_regression_2024_08_22/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  54559958 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_stress_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @  54559958 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_alert_reset_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 8.aes_stress_all_with_rand_reset.98404754105448543490863936086673220086399974816976817401263989013682732441852
    Line 956, in log /workspaces/repo/scratch/os_regression_2024_08_22/aes_masked-sim-xcelium/8.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 1357483473 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 1357483473 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_ctr_fi_vseq.sv:59) [aes_ctr_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_ctr_fi has 1 failures.
  - 15.aes_ctr_fi.84728310669774638655051285437507929715426782597511822393889265963615250035400
    Line 129, in log /workspaces/repo/scratch/os_regression_2024_08_22/aes_masked-sim-xcelium/15.aes_ctr_fi/latest/run.log
```
  UVM_FATAL @ 10014122076 ps: (aes_ctr_fi_vseq.sv:59) [uvm_test_top.env.virtual_sequencer.aes_ctr_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10014122076 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```