AES/UNMASKED Simulation Results

Monday May 22 2023 07:05:49 UTC

GitHub Revision: `e3fb01b5e`

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 3641199223

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	57.592us	1	1	100.00
V1	smoke	aes_smoke	6.000s	146.925us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	83.869us	5	5	100.00
V1	csr_rw	aes_csr_rw	5.000s	82.283us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	11.000s	1.663ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	7.000s	920.651us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	4.000s	130.435us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	5.000s	82.283us	20	20	100.00
		aes_csr_aliasing	7.000s	920.651us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	6.000s	146.925us	50	50	100.00
		aes_config_error	6.000s	97.031us	50	50	100.00
		aes_stress	38.000s	5.840ms	50	50	100.00
V2	key_length	aes_smoke	6.000s	146.925us	50	50	100.00
		aes_config_error	6.000s	97.031us	50	50	100.00
		aes_stress	38.000s	5.840ms	50	50	100.00
V2	back2back	aes_stress	38.000s	5.840ms	50	50	100.00
		aes_b2b	11.000s	986.740us	50	50	100.00
V2	backpressure	aes_stress	38.000s	5.840ms	50	50	100.00
V2	multi_message	aes_smoke	6.000s	146.925us	50	50	100.00
		aes_config_error	6.000s	97.031us	50	50	100.00
		aes_stress	38.000s	5.840ms	50	50	100.00
		aes_alert_reset	5.000s	75.568us	50	50	100.00
V2	failure_test	aes_config_error	6.000s	97.031us	50	50	100.00
		aes_alert_reset	5.000s	75.568us	50	50	100.00
		aes_man_cfg_err	4.000s	59.135us	50	50	100.00
V2	trigger_clear_test	aes_clear	7.000s	176.500us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	6.000s	359.984us	1	1	100.00
V2	reset_recovery	aes_alert_reset	5.000s	75.568us	50	50	100.00
V2	stress	aes_stress	38.000s	5.840ms	50	50	100.00
V2	sideload	aes_stress	38.000s	5.840ms	50	50	100.00
		aes_sideload	5.000s	61.523us	50	50	100.00
V2	deinitialization	aes_deinit	5.000s	61.510us	50	50	100.00
V2	alert_test	aes_alert_test	4.000s	66.181us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	6.000s	155.967us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	6.000s	155.967us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	83.869us	5	5	100.00
		aes_csr_rw	5.000s	82.283us	20	20	100.00
		aes_csr_aliasing	7.000s	920.651us	5	5	100.00
		aes_same_csr_outstanding	5.000s	65.636us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	83.869us	5	5	100.00
		aes_csr_rw	5.000s	82.283us	20	20	100.00
		aes_csr_aliasing	7.000s	920.651us	5	5	100.00
		aes_same_csr_outstanding	5.000s	65.636us	20	20	100.00
V2		TOTAL			491	491	100.00
V2S	reseeding	aes_reseed	42.000s	1.002ms	49	50	98.00
V2S	fault_inject	aes_fi	7.000s	239.618us	50	50	100.00
		aes_control_fi	55.000s	63.029ms	269	300	89.67
		aes_cipher_fi	54.000s	31.531ms	317	350	90.57
V2S	shadow_reg_update_error	aes_shadow_reg_errors	5.000s	166.271us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	5.000s	166.271us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	5.000s	166.271us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	5.000s	166.271us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	7.000s	355.075us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	6.000s	386.519us	5	5	100.00
		aes_tl_intg_err	6.000s	316.962us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	6.000s	316.962us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	5.000s	75.568us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	5.000s	166.271us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	6.000s	146.925us	50	50	100.00
		aes_stress	38.000s	5.840ms	50	50	100.00
		aes_alert_reset	5.000s	75.568us	50	50	100.00
		aes_core_fi	6.533m	10.010ms	65	70	92.86
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	5.000s	166.271us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_stress	38.000s	5.840ms	50	50	100.00
		aes_readability	4.000s	157.425us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	38.000s	5.840ms	50	50	100.00
		aes_sideload	5.000s	61.523us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	4.000s	157.425us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	4.000s	157.425us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	4.000s	157.425us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	4.000s	157.425us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	4.000s	157.425us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	38.000s	5.840ms	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	38.000s	5.840ms	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	7.000s	239.618us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	7.000s	239.618us	50	50	100.00
		aes_control_fi	55.000s	63.029ms	269	300	89.67
		aes_cipher_fi	54.000s	31.531ms	317	350	90.57
		aes_ctr_fi	4.000s	90.274us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	7.000s	239.618us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	7.000s	239.618us	50	50	100.00
		aes_control_fi	55.000s	63.029ms	269	300	89.67
		aes_cipher_fi	54.000s	31.531ms	317	350	90.57
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	54.000s	31.531ms	317	350	90.57
V2S	sec_cm_ctr_fsm_sparse	aes_fi	7.000s	239.618us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	7.000s	239.618us	50	50	100.00
		aes_control_fi	55.000s	63.029ms	269	300	89.67
		aes_ctr_fi	4.000s	90.274us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	7.000s	239.618us	50	50	100.00
		aes_control_fi	55.000s	63.029ms	269	300	89.67
		aes_cipher_fi	54.000s	31.531ms	317	350	90.57
		aes_ctr_fi	4.000s	90.274us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	5.000s	75.568us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	7.000s	239.618us	50	50	100.00
		aes_control_fi	55.000s	63.029ms	269	300	89.67
		aes_cipher_fi	54.000s	31.531ms	317	350	90.57
		aes_ctr_fi	4.000s	90.274us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	7.000s	239.618us	50	50	100.00
		aes_control_fi	55.000s	63.029ms	269	300	89.67
		aes_cipher_fi	54.000s	31.531ms	317	350	90.57
		aes_ctr_fi	4.000s	90.274us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	7.000s	239.618us	50	50	100.00
		aes_control_fi	55.000s	63.029ms	269	300	89.67
		aes_ctr_fi	4.000s	90.274us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	7.000s	239.618us	50	50	100.00
		aes_control_fi	55.000s	63.029ms	269	300	89.67
		aes_cipher_fi	54.000s	31.531ms	317	350	90.57
V2S		TOTAL			915	985	92.89
V3		TOTAL			0	0	--
		TOTAL			1512	1582	95.58

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	12	12	12	100.00
V2S	11	11	7	63.64

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.10	97.58	94.52	98.75	93.68	97.72	91.11	98.07	91.28

Failure Buckets

Job aes_unmasked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 39 failures:
- Test aes_cipher_fi has 22 failures.
  - 13.aes_cipher_fi.1856196534
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/13.aes_cipher_fi/latest/run.log
```
  Job ID: smart:35113e5a-043d-43e3-a93b-4a8996055303
```
  - 20.aes_cipher_fi.3768456802
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/20.aes_cipher_fi/latest/run.log
```
  Job ID: smart:1b289d42-9fb8-4ed2-a81a-3fdd89046f7a
```
  - ... and 20 more failures.
- Test aes_control_fi has 17 failures.
  - 22.aes_control_fi.3593530572
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/22.aes_control_fi/latest/run.log
```
  Job ID: smart:cca44d83-9883-4611-acb9-d911687c29d9
```
  - 27.aes_control_fi.4095175573
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/27.aes_control_fi/latest/run.log
```
  Job ID: smart:8d8d0894-874c-43cd-ac63-e1055930fa71
```
  - ... and 15 more failures.

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 14 failures:

Test aes_control_fi has 14 failures.

3.aes_control_fi.1227173974
Line 280, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/3.aes_control_fi/latest/run.log

  UVM_FATAL @ 10007039788 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10007039788 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

34.aes_control_fi.2247128713
Line 279, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/34.aes_control_fi/latest/run.log

  UVM_FATAL @ 10005110608 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10005110608 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 12 more failures.

UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 11 failures:

Test aes_cipher_fi has 11 failures.

21.aes_cipher_fi.1577943579
Line 273, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/21.aes_cipher_fi/latest/run.log

  UVM_FATAL @ 10013216823 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10013216823 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

34.aes_cipher_fi.929678247
Line 285, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/34.aes_cipher_fi/latest/run.log

  UVM_FATAL @ 10010237040 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10010237040 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 9 more failures.

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 3 failures:

Test aes_core_fi has 3 failures.

20.aes_core_fi.1566890098
Line 272, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/20.aes_core_fi/latest/run.log

  UVM_FATAL @ 10007897354 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10007897354 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

27.aes_core_fi.325696619
Line 276, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/27.aes_core_fi/latest/run.log

  UVM_FATAL @ 10007622694 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10007622694 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL (aes_scoreboard.sv:621) scoreboard [scoreboard] # * has 1 failures:

Test aes_reseed has 1 failures.

41.aes_reseed.3386120165
Line 2406, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/41.aes_reseed/latest/run.log

  UVM_FATAL @  77598184 ps: (aes_scoreboard.sv:621) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]  # 0
            TEST FAILED MESSAGES DID NOT MATCH
  
                 0 d0      9f      55      0
                 1 00      4c      1b      0

UVM_FATAL (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=*) == * has 1 failures:
- Test aes_core_fi has 1 failures.
  - 41.aes_core_fi.2369276377
    Line 275, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/41.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10010259142 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0xd3664284) == 0x0
  UVM_INFO @ 10010259142 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:89) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 57.aes_core_fi.1708785289
    Line 270, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/57.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10057628407 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10057628407 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```