AES/UNMASKED Simulation Results

Sunday January 07 2024 20:02:41 UTC

GitHub Revision: `042415198f`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 94802583296605211241780338187580260959003534163885373932116464911642413280689

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	64.003us	1	1	100.00
V1	smoke	aes_smoke	8.000s	55.057us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	8.000s	68.628us	5	5	100.00
V1	csr_rw	aes_csr_rw	8.000s	80.781us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	8.000s	181.618us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	15.000s	161.425us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	8.000s	73.433us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	8.000s	80.781us	20	20	100.00
		aes_csr_aliasing	15.000s	161.425us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	8.000s	55.057us	50	50	100.00
		aes_config_error	8.000s	164.065us	50	50	100.00
		aes_stress	8.000s	69.696us	50	50	100.00
V2	key_length	aes_smoke	8.000s	55.057us	50	50	100.00
		aes_config_error	8.000s	164.065us	50	50	100.00
		aes_stress	8.000s	69.696us	50	50	100.00
V2	back2back	aes_stress	8.000s	69.696us	50	50	100.00
		aes_b2b	12.000s	137.069us	50	50	100.00
V2	backpressure	aes_stress	8.000s	69.696us	50	50	100.00
V2	multi_message	aes_smoke	8.000s	55.057us	50	50	100.00
		aes_config_error	8.000s	164.065us	50	50	100.00
		aes_stress	8.000s	69.696us	50	50	100.00
		aes_alert_reset	9.000s	113.113us	50	50	100.00
V2	failure_test	aes_man_cfg_err	15.000s	75.991us	50	50	100.00
		aes_config_error	8.000s	164.065us	50	50	100.00
		aes_alert_reset	9.000s	113.113us	50	50	100.00
V2	trigger_clear_test	aes_clear	7.000s	89.949us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	7.000s	818.174us	1	1	100.00
V2	reset_recovery	aes_alert_reset	9.000s	113.113us	50	50	100.00
V2	stress	aes_stress	8.000s	69.696us	50	50	100.00
V2	sideload	aes_stress	8.000s	69.696us	50	50	100.00
		aes_sideload	9.000s	105.091us	50	50	100.00
V2	deinitialization	aes_deinit	6.000s	324.874us	50	50	100.00
V2	stress_all	aes_stress_all	26.000s	1.799ms	9	10	90.00
V2	alert_test	aes_alert_test	8.000s	52.364us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	10.000s	142.865us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	10.000s	142.865us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	8.000s	68.628us	5	5	100.00
		aes_csr_rw	8.000s	80.781us	20	20	100.00
		aes_csr_aliasing	15.000s	161.425us	5	5	100.00
		aes_same_csr_outstanding	4.000s	128.035us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	8.000s	68.628us	5	5	100.00
		aes_csr_rw	8.000s	80.781us	20	20	100.00
		aes_csr_aliasing	15.000s	161.425us	5	5	100.00
		aes_same_csr_outstanding	4.000s	128.035us	20	20	100.00
V2		TOTAL			500	501	99.80
V2S	reseeding	aes_reseed	15.000s	149.146us	50	50	100.00
V2S	fault_inject	aes_fi	14.000s	206.564us	50	50	100.00
		aes_control_fi	50.000s	47.758ms	275	300	91.67
		aes_cipher_fi	49.000s	15.949ms	318	350	90.86
V2S	shadow_reg_update_error	aes_shadow_reg_errors	8.000s	88.791us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	8.000s	88.791us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	8.000s	88.791us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	8.000s	88.791us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	14.000s	339.713us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	5.000s	453.057us	5	5	100.00
		aes_tl_intg_err	8.000s	127.757us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	8.000s	127.757us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	9.000s	113.113us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	8.000s	88.791us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	8.000s	55.057us	50	50	100.00
		aes_stress	8.000s	69.696us	50	50	100.00
		aes_alert_reset	9.000s	113.113us	50	50	100.00
		aes_core_fi	9.000s	62.195us	70	70	100.00
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	8.000s	88.791us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	5.000s	314.932us	50	50	100.00
		aes_stress	8.000s	69.696us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	8.000s	69.696us	50	50	100.00
		aes_sideload	9.000s	105.091us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	5.000s	314.932us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	5.000s	314.932us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	5.000s	314.932us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	5.000s	314.932us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	5.000s	314.932us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	8.000s	69.696us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	8.000s	69.696us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	14.000s	206.564us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	14.000s	206.564us	50	50	100.00
		aes_control_fi	50.000s	47.758ms	275	300	91.67
		aes_cipher_fi	49.000s	15.949ms	318	350	90.86
		aes_ctr_fi	8.000s	96.366us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	14.000s	206.564us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	14.000s	206.564us	50	50	100.00
		aes_control_fi	50.000s	47.758ms	275	300	91.67
		aes_cipher_fi	49.000s	15.949ms	318	350	90.86
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	49.000s	15.949ms	318	350	90.86
V2S	sec_cm_ctr_fsm_sparse	aes_fi	14.000s	206.564us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	14.000s	206.564us	50	50	100.00
		aes_control_fi	50.000s	47.758ms	275	300	91.67
		aes_ctr_fi	8.000s	96.366us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	14.000s	206.564us	50	50	100.00
		aes_control_fi	50.000s	47.758ms	275	300	91.67
		aes_cipher_fi	49.000s	15.949ms	318	350	90.86
		aes_ctr_fi	8.000s	96.366us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	9.000s	113.113us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	14.000s	206.564us	50	50	100.00
		aes_control_fi	50.000s	47.758ms	275	300	91.67
		aes_cipher_fi	49.000s	15.949ms	318	350	90.86
		aes_ctr_fi	8.000s	96.366us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	14.000s	206.564us	50	50	100.00
		aes_control_fi	50.000s	47.758ms	275	300	91.67
		aes_cipher_fi	49.000s	15.949ms	318	350	90.86
		aes_ctr_fi	8.000s	96.366us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	14.000s	206.564us	50	50	100.00
		aes_control_fi	50.000s	47.758ms	275	300	91.67
		aes_ctr_fi	8.000s	96.366us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	14.000s	206.564us	50	50	100.00
		aes_control_fi	50.000s	47.758ms	275	300	91.67
		aes_cipher_fi	49.000s	15.949ms	318	350	90.86
V2S		TOTAL			928	985	94.21
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	2.000m	10.105ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1534	1602	95.76

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	12	92.31
V2S	11	11	9	81.82
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.25	97.52	94.39	98.81	93.76	97.72	91.11	98.66	98.38

Failure Buckets

Job aes_unmasked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 37 failures:
- Test aes_cipher_fi has 23 failures.
  - 11.aes_cipher_fi.853949673341642655250838310683545342511670772902984844189909903327443805896
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/11.aes_cipher_fi/latest/run.log
```
  Job ID: smart:527f8957-174a-4602-9f66-5299de29c3d1
```
  - 23.aes_cipher_fi.108984965656796525877806365962652794502457983622773741927668273953262368074182
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/23.aes_cipher_fi/latest/run.log
```
  Job ID: smart:fbdc4f34-dcfd-4fb7-86f2-30ebcda450b9
```
  - ... and 21 more failures.
- Test aes_control_fi has 14 failures.
  - 23.aes_control_fi.26959770399492306607795807873388490292740355084694929922226809539985580610176
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/23.aes_control_fi/latest/run.log
```
  Job ID: smart:40fc8b6e-6d9c-46b5-ba88-6014defa8905
```
  - 40.aes_control_fi.112805569896933148247817267623960932318230759125061663891349993978173483230303
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/40.aes_control_fi/latest/run.log
```
  Job ID: smart:554978d6-1000-4211-a0cc-ba39dc116616
```
  - ... and 12 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 11 failures:
- Test aes_control_fi has 11 failures.
  - 4.aes_control_fi.89194123732049707916093551667859468700927520356183254079469764233640782119708
    Line 324, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/4.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10017854011 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10017854011 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 46.aes_control_fi.43250123878189644429356068199767628010239024605542697329536756974670462907428
    Line 321, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/46.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10038967375 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10038967375 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 9 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 9 failures:
- Test aes_cipher_fi has 9 failures.
  - 33.aes_cipher_fi.48251785932301680527233452515069209673368309666334119690744278947113341695457
    Line 324, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/33.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10004314038 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10004314038 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 52.aes_cipher_fi.53110922295475634514938271444625602853770524585575786256260075227028122324727
    Line 315, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/52.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10007451723 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10007451723 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 7 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 7 failures:

Test aes_stress_all_with_rand_reset has 7 failures.

0.aes_stress_all_with_rand_reset.106180521200017662158665145060202834300687779397837853754872978349090965907189
Line 665, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 10105096258 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 10105096258 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.4875140125871487274044702813209518217741489140599568182791701517101509459115
Line 1639, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1698654528 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1698654528 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 2 failures:

Test aes_stress_all_with_rand_reset has 2 failures.

7.aes_stress_all_with_rand_reset.69762001890853240052332471553713976335980850681257351808308246828263573253833
Line 1719, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/7.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1104711461 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1104711461 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

9.aes_stress_all_with_rand_reset.99368212951888300810799945275625534878564549308623536468386484512143577244318
Line 488, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/9.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 405384064 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 405384064 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,984): Assertion AesSecCmDataRegLocalEscIv has failed (* cycles, starting * PS) has 1 failures:
- Test aes_stress_all has 1 failures.
  - 2.aes_stress_all.102987957226723723550721745082776419618419710141829347284780256480077900941877
    Line 38032, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/2.aes_stress_all/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,984): (time 2935810462 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 2935760462 PS)
  UVM_ERROR @ 2935810462 ps: (aes_core.sv:984) [ASSERT FAILED] AesSecCmDataRegLocalEscIv
  UVM_INFO @ 2935810462 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:520) [aes_alert_reset_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_fault fired unexpectedly! has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 8.aes_stress_all_with_rand_reset.100896073510671248398743484840558341558207456739427539743511201898746476501956
    Line 763, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/8.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 923012222 ps: (cip_base_vseq.sv:520) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_fault fired unexpectedly!
  UVM_INFO @ 923012222 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```