AES/UNMASKED Simulation Results

Sunday February 18 2024 20:02:30 UTC

GitHub Revision: `8faf04697a`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 18983509472502570446328716692660256492766541929441074968843370054317032656232

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	56.196us	1	1	100.00
V1	smoke	aes_smoke	9.000s	149.984us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	4.000s	51.567us	5	5	100.00
V1	csr_rw	aes_csr_rw	4.000s	203.912us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	9.000s	321.231us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	161.824us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	6.000s	254.711us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	4.000s	203.912us	20	20	100.00
		aes_csr_aliasing	5.000s	161.824us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	9.000s	149.984us	50	50	100.00
		aes_config_error	6.000s	64.365us	50	50	100.00
		aes_stress	5.000s	149.445us	50	50	100.00
V2	key_length	aes_smoke	9.000s	149.984us	50	50	100.00
		aes_config_error	6.000s	64.365us	50	50	100.00
		aes_stress	5.000s	149.445us	50	50	100.00
V2	back2back	aes_stress	5.000s	149.445us	50	50	100.00
		aes_b2b	11.000s	1.435ms	50	50	100.00
V2	backpressure	aes_stress	5.000s	149.445us	50	50	100.00
V2	multi_message	aes_smoke	9.000s	149.984us	50	50	100.00
		aes_config_error	6.000s	64.365us	50	50	100.00
		aes_stress	5.000s	149.445us	50	50	100.00
		aes_alert_reset	5.000s	148.062us	50	50	100.00
V2	failure_test	aes_man_cfg_err	4.000s	58.283us	50	50	100.00
		aes_config_error	6.000s	64.365us	50	50	100.00
		aes_alert_reset	5.000s	148.062us	50	50	100.00
V2	trigger_clear_test	aes_clear	9.000s	251.187us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	6.000s	214.259us	1	1	100.00
V2	reset_recovery	aes_alert_reset	5.000s	148.062us	50	50	100.00
V2	stress	aes_stress	5.000s	149.445us	50	50	100.00
V2	sideload	aes_stress	5.000s	149.445us	50	50	100.00
		aes_sideload	5.000s	314.257us	50	50	100.00
V2	deinitialization	aes_deinit	8.000s	235.438us	50	50	100.00
V2	stress_all	aes_stress_all	34.000s	2.733ms	10	10	100.00
V2	alert_test	aes_alert_test	6.000s	67.855us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	6.000s	226.995us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	6.000s	226.995us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	4.000s	51.567us	5	5	100.00
		aes_csr_rw	4.000s	203.912us	20	20	100.00
		aes_csr_aliasing	5.000s	161.824us	5	5	100.00
		aes_same_csr_outstanding	4.000s	206.393us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	4.000s	51.567us	5	5	100.00
		aes_csr_rw	4.000s	203.912us	20	20	100.00
		aes_csr_aliasing	5.000s	161.824us	5	5	100.00
		aes_same_csr_outstanding	4.000s	206.393us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	8.000s	63.054us	50	50	100.00
V2S	fault_inject	aes_fi	13.000s	74.918us	49	50	98.00
		aes_control_fi	43.000s	15.785ms	282	300	94.00
		aes_cipher_fi	49.000s	10.003ms	321	350	91.71
V2S	shadow_reg_update_error	aes_shadow_reg_errors	7.000s	70.322us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	7.000s	70.322us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	7.000s	70.322us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	7.000s	70.322us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	4.000s	243.169us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	7.000s	1.870ms	5	5	100.00
		aes_tl_intg_err	5.000s	265.944us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	5.000s	265.944us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	5.000s	148.062us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	7.000s	70.322us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	9.000s	149.984us	50	50	100.00
		aes_stress	5.000s	149.445us	50	50	100.00
		aes_alert_reset	5.000s	148.062us	50	50	100.00
		aes_core_fi	1.483m	10.048ms	63	70	90.00
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	7.000s	70.322us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	4.000s	60.113us	50	50	100.00
		aes_stress	5.000s	149.445us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	5.000s	149.445us	50	50	100.00
		aes_sideload	5.000s	314.257us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	4.000s	60.113us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	4.000s	60.113us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	4.000s	60.113us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	4.000s	60.113us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	4.000s	60.113us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	5.000s	149.445us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	5.000s	149.445us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	13.000s	74.918us	49	50	98.00
V2S	sec_cm_main_fsm_redun	aes_fi	13.000s	74.918us	49	50	98.00
		aes_control_fi	43.000s	15.785ms	282	300	94.00
		aes_cipher_fi	49.000s	10.003ms	321	350	91.71
		aes_ctr_fi	8.000s	171.851us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	13.000s	74.918us	49	50	98.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	13.000s	74.918us	49	50	98.00
		aes_control_fi	43.000s	15.785ms	282	300	94.00
		aes_cipher_fi	49.000s	10.003ms	321	350	91.71
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	49.000s	10.003ms	321	350	91.71
V2S	sec_cm_ctr_fsm_sparse	aes_fi	13.000s	74.918us	49	50	98.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	13.000s	74.918us	49	50	98.00
		aes_control_fi	43.000s	15.785ms	282	300	94.00
		aes_ctr_fi	8.000s	171.851us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	13.000s	74.918us	49	50	98.00
		aes_control_fi	43.000s	15.785ms	282	300	94.00
		aes_cipher_fi	49.000s	10.003ms	321	350	91.71
		aes_ctr_fi	8.000s	171.851us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	5.000s	148.062us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	13.000s	74.918us	49	50	98.00
		aes_control_fi	43.000s	15.785ms	282	300	94.00
		aes_cipher_fi	49.000s	10.003ms	321	350	91.71
		aes_ctr_fi	8.000s	171.851us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	13.000s	74.918us	49	50	98.00
		aes_control_fi	43.000s	15.785ms	282	300	94.00
		aes_cipher_fi	49.000s	10.003ms	321	350	91.71
		aes_ctr_fi	8.000s	171.851us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	13.000s	74.918us	49	50	98.00
		aes_control_fi	43.000s	15.785ms	282	300	94.00
		aes_ctr_fi	8.000s	171.851us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	13.000s	74.918us	49	50	98.00
		aes_control_fi	43.000s	15.785ms	282	300	94.00
		aes_cipher_fi	49.000s	10.003ms	321	350	91.71
V2S		TOTAL			930	985	94.42
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	3.933m	34.972ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1537	1602	95.94

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	13	100.00
V2S	11	11	7	63.64
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.17	97.42	94.16	98.83	93.62	97.72	91.11	98.85	97.01

Failure Buckets

Job aes_unmasked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 29 failures:
- Test aes_control_fi has 14 failures.
  - 7.aes_control_fi.25525631116914696009313445859256637438947091048638881936044583342482605032906
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/7.aes_control_fi/latest/run.log
```
  Job ID: smart:b19a8264-5df5-4641-84e7-2868f6258232
```
  - 10.aes_control_fi.40429718567376675777595797440475434990320485147206701949560014873610999005341
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/10.aes_control_fi/latest/run.log
```
  Job ID: smart:08ddc1ef-b9c6-4bb7-af31-e7bbba9278e9
```
  - ... and 12 more failures.
- Test aes_cipher_fi has 15 failures.
  - 20.aes_cipher_fi.7347235760915433804452171182174353875238888095989295207522175954237817598802
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/20.aes_cipher_fi/latest/run.log
```
  Job ID: smart:2bbb21e6-1c3e-418e-85f2-390de0ab321f
```
  - 27.aes_cipher_fi.21983388864912359847692832057029074027434625841545585005097065668162710230857
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/27.aes_cipher_fi/latest/run.log
```
  Job ID: smart:b9c3d5bf-92ff-4a17-9f96-9c553f99756a
```
  - ... and 13 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 14 failures:
- Test aes_cipher_fi has 14 failures.
  - 14.aes_cipher_fi.93057574379992730852583537248058606640086610280133752457286223147098636966685
    Line 326, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/14.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10018654650 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10018654650 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 24.aes_cipher_fi.5456081750946245742530440203057845221079981827280994064169025663659497387674
    Line 316, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/24.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10003259676 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10003259676 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 12 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 9 failures:

Test aes_stress_all_with_rand_reset has 9 failures.

0.aes_stress_all_with_rand_reset.26373410760010168792415971664162907757786777461962774490414143903439177749274
Line 513, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 188692197 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 188692197 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.40918901952323737874785204001985572397468977547439771765136695548146458404182
Line 842, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 34972498132 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 34972498132 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 7 more failures.

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 5 failures:
- Test aes_core_fi has 5 failures.
  - 8.aes_core_fi.106035733860687420576143900585338767369981598279968627696529196260393534901602
    Line 324, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/8.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10010116544 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10010116544 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 14.aes_core_fi.33797042492900842577643229704219879281015191100055638873969659124802553517321
    Line 328, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/14.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10012965982 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10012965982 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 4 failures:
- Test aes_control_fi has 4 failures.
  - 93.aes_control_fi.27625128305724975366299022694365123531644332980591029496676207011966733045228
    Line 325, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/93.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10010143584 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10010143584 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 115.aes_control_fi.1042360177376759532867467210478778125066970969464763677874454174607677759078
    Line 315, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/115.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10011945089 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10011945089 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
UVM_ERROR (cip_base_vseq.sv:520) [aes_alert_reset_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_fault fired unexpectedly! has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 2.aes_stress_all_with_rand_reset.57055544679668307711033444681373363908432854169159507816231563699164356276190
    Line 394, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 209658919 ps: (cip_base_vseq.sv:520) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_fault fired unexpectedly!
  UVM_INFO @ 209658919 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:89) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 11.aes_core_fi.18009067108897181312895150947475320962114932597521069083483684690677150644060
    Line 316, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/11.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10023632225 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10023632225 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_fi_vseq.sv:69) virtual_sequencer [aes_fi_vseq] Was Able to finish without clearing reset has 1 failures:
- Test aes_fi has 1 failures.
  - 24.aes_fi.11421408658962039167450343740529316597984825046637653131518817870093846228786
    Line 6678, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/24.aes_fi/latest/run.log
```
  UVM_FATAL @ 102696085 ps: (aes_fi_vseq.sv:69) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.aes_fi_vseq] Was Able to finish without clearing reset
  UVM_INFO @ 102696085 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:572) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=*) == * has 1 failures:
- Test aes_core_fi has 1 failures.
  - 32.aes_core_fi.12203511251571804224303392543107605921173703993716630529246467062201907721632
    Line 316, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/32.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10047539211 ps: (csr_utils_pkg.sv:572) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0xd8290384) == 0x0
  UVM_INFO @ 10047539211 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```