AES/UNMASKED Simulation Results

Wednesday February 21 2024 20:04:41 UTC

GitHub Revision: `df66f8a42e`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 105428938048998514387352931012238053576571450380985277214810281406530880002461

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	2.000s	89.213us	1	1	100.00
V1	smoke	aes_smoke	13.000s	85.438us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	4.000s	51.502us	5	5	100.00
V1	csr_rw	aes_csr_rw	13.000s	59.393us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	12.000s	1.540ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	9.000s	328.177us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	5.000s	553.737us	19	20	95.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	13.000s	59.393us	20	20	100.00
		aes_csr_aliasing	9.000s	328.177us	5	5	100.00
V1		TOTAL			105	106	99.06
V2	algorithm	aes_smoke	13.000s	85.438us	50	50	100.00
		aes_config_error	9.000s	76.814us	50	50	100.00
		aes_stress	6.000s	85.382us	50	50	100.00
V2	key_length	aes_smoke	13.000s	85.438us	50	50	100.00
		aes_config_error	9.000s	76.814us	50	50	100.00
		aes_stress	6.000s	85.382us	50	50	100.00
V2	back2back	aes_stress	6.000s	85.382us	50	50	100.00
		aes_b2b	16.000s	347.699us	50	50	100.00
V2	backpressure	aes_stress	6.000s	85.382us	50	50	100.00
V2	multi_message	aes_smoke	13.000s	85.438us	50	50	100.00
		aes_config_error	9.000s	76.814us	50	50	100.00
		aes_stress	6.000s	85.382us	50	50	100.00
		aes_alert_reset	8.000s	341.247us	49	50	98.00
V2	failure_test	aes_man_cfg_err	8.000s	86.431us	50	50	100.00
		aes_config_error	9.000s	76.814us	50	50	100.00
		aes_alert_reset	8.000s	341.247us	49	50	98.00
V2	trigger_clear_test	aes_clear	9.000s	93.175us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	7.000s	370.157us	1	1	100.00
V2	reset_recovery	aes_alert_reset	8.000s	341.247us	49	50	98.00
V2	stress	aes_stress	6.000s	85.382us	50	50	100.00
V2	sideload	aes_stress	6.000s	85.382us	50	50	100.00
		aes_sideload	8.000s	66.229us	50	50	100.00
V2	deinitialization	aes_deinit	8.000s	96.367us	50	50	100.00
V2	stress_all	aes_stress_all	35.000s	710.974us	9	10	90.00
V2	alert_test	aes_alert_test	11.000s	63.988us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	17.000s	148.829us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	17.000s	148.829us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	4.000s	51.502us	5	5	100.00
		aes_csr_rw	13.000s	59.393us	20	20	100.00
		aes_csr_aliasing	9.000s	328.177us	5	5	100.00
		aes_same_csr_outstanding	1.867m	10.027ms	19	20	95.00
V2	tl_d_partial_access	aes_csr_hw_reset	4.000s	51.502us	5	5	100.00
		aes_csr_rw	13.000s	59.393us	20	20	100.00
		aes_csr_aliasing	9.000s	328.177us	5	5	100.00
		aes_same_csr_outstanding	1.867m	10.027ms	19	20	95.00
V2		TOTAL			498	501	99.40
V2S	reseeding	aes_reseed	10.000s	293.667us	50	50	100.00
V2S	fault_inject	aes_fi	9.000s	239.329us	50	50	100.00
		aes_control_fi	50.000s	10.003ms	271	300	90.33
		aes_cipher_fi	51.000s	31.530ms	328	350	93.71
V2S	shadow_reg_update_error	aes_shadow_reg_errors	12.000s	176.757us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	12.000s	176.757us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	12.000s	176.757us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	12.000s	176.757us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	13.000s	140.360us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	9.000s	260.786us	5	5	100.00
		aes_tl_intg_err	9.000s	170.298us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	9.000s	170.298us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	8.000s	341.247us	49	50	98.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	12.000s	176.757us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	13.000s	85.438us	50	50	100.00
		aes_stress	6.000s	85.382us	50	50	100.00
		aes_alert_reset	8.000s	341.247us	49	50	98.00
		aes_core_fi	6.950m	10.010ms	64	70	91.43
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	12.000s	176.757us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	8.000s	91.416us	50	50	100.00
		aes_stress	6.000s	85.382us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	6.000s	85.382us	50	50	100.00
		aes_sideload	8.000s	66.229us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	8.000s	91.416us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	8.000s	91.416us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	8.000s	91.416us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	8.000s	91.416us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	8.000s	91.416us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	6.000s	85.382us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	6.000s	85.382us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	9.000s	239.329us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	9.000s	239.329us	50	50	100.00
		aes_control_fi	50.000s	10.003ms	271	300	90.33
		aes_cipher_fi	51.000s	31.530ms	328	350	93.71
		aes_ctr_fi	8.000s	86.640us	49	50	98.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	9.000s	239.329us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	9.000s	239.329us	50	50	100.00
		aes_control_fi	50.000s	10.003ms	271	300	90.33
		aes_cipher_fi	51.000s	31.530ms	328	350	93.71
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	51.000s	31.530ms	328	350	93.71
V2S	sec_cm_ctr_fsm_sparse	aes_fi	9.000s	239.329us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	9.000s	239.329us	50	50	100.00
		aes_control_fi	50.000s	10.003ms	271	300	90.33
		aes_ctr_fi	8.000s	86.640us	49	50	98.00
V2S	sec_cm_ctrl_sparse	aes_fi	9.000s	239.329us	50	50	100.00
		aes_control_fi	50.000s	10.003ms	271	300	90.33
		aes_cipher_fi	51.000s	31.530ms	328	350	93.71
		aes_ctr_fi	8.000s	86.640us	49	50	98.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	8.000s	341.247us	49	50	98.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	9.000s	239.329us	50	50	100.00
		aes_control_fi	50.000s	10.003ms	271	300	90.33
		aes_cipher_fi	51.000s	31.530ms	328	350	93.71
		aes_ctr_fi	8.000s	86.640us	49	50	98.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	9.000s	239.329us	50	50	100.00
		aes_control_fi	50.000s	10.003ms	271	300	90.33
		aes_cipher_fi	51.000s	31.530ms	328	350	93.71
		aes_ctr_fi	8.000s	86.640us	49	50	98.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	9.000s	239.329us	50	50	100.00
		aes_control_fi	50.000s	10.003ms	271	300	90.33
		aes_ctr_fi	8.000s	86.640us	49	50	98.00
V2S	sec_cm_data_reg_local_esc	aes_fi	9.000s	239.329us	50	50	100.00
		aes_control_fi	50.000s	10.003ms	271	300	90.33
		aes_cipher_fi	51.000s	31.530ms	328	350	93.71
V2S		TOTAL			927	985	94.11
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	1.267m	3.305ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1530	1602	95.51

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	6	85.71
V2	13	13	10	76.92
V2S	11	11	7	63.64
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.24	97.51	94.37	98.87	93.79	97.64	93.33	98.66	96.01

Failure Buckets

Job aes_unmasked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 36 failures:
- Test aes_cipher_fi has 13 failures.
  - 6.aes_cipher_fi.31193482683493989223143320419404989764473474261692909638337889661126366345624
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/6.aes_cipher_fi/latest/run.log
```
  Job ID: smart:f26c11d8-e204-48d2-96b1-6f0dea2599cb
```
  - 11.aes_cipher_fi.66069715698988046724630969321368524090377376433589698861747703505187034963326
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/11.aes_cipher_fi/latest/run.log
```
  Job ID: smart:fac0294d-d17b-4afa-af2c-da00e07b3749
```
  - ... and 11 more failures.
- Test aes_control_fi has 22 failures.
  - 7.aes_control_fi.19199585807974690341363359999976671359382388555092928009297595663905266073069
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/7.aes_control_fi/latest/run.log
```
  Job ID: smart:b1fdb4c2-1ab1-40eb-b165-e26dc050303f
```
  - 12.aes_control_fi.92149357843707387814209359096977373404281238158534155294842012540363290202988
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/12.aes_control_fi/latest/run.log
```
  Job ID: smart:f7180349-3a1b-4add-9599-ba7f453d44bd
```
  - ... and 20 more failures.
- Test aes_ctr_fi has 1 failures.
  - 47.aes_ctr_fi.2837116989129209651311847584770257900732504979679509547200460786772687246188
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/47.aes_ctr_fi/latest/run.log
```
  Job ID: smart:8f0206ad-3587-46bb-ba92-7086b5a05d91
```
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 9 failures:
- Test aes_cipher_fi has 9 failures.
  - 42.aes_cipher_fi.25790974792371963589545592604547815310626277035743530560652847556056020477603
    Line 315, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/42.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10006167013 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006167013 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 101.aes_cipher_fi.23234847385794295246660387436724996327470788008615158921877900111872368176061
    Line 324, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/101.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10002691784 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10002691784 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 7 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 7 failures:

Test aes_stress_all_with_rand_reset has 7 failures.

1.aes_stress_all_with_rand_reset.114795411710175570554518435605380124285628215595712615068954608976713736447816
Line 441, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 7035272454 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 7035272454 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.aes_stress_all_with_rand_reset.33368079798372898096087938301390664987291881180164400778059886955842943324071
Line 1045, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 473572958 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 473572958 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 7 failures:
- Test aes_control_fi has 7 failures.
  - 75.aes_control_fi.114310178592417077631164557112503203433888526748304355767030570662888335430978
    Line 314, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/75.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10003605115 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10003605115 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 79.aes_control_fi.50434822544384423090428101610618663373537309547758690459237688264679251635328
    Line 311, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/79.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10003909220 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10003909220 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 3 failures:
- Test aes_core_fi has 3 failures.
  - 25.aes_core_fi.2754096765581222986231883895936978439630657835920332005421024776592498101886
    Line 316, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/25.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10010508934 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10010508934 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 31.aes_core_fi.69822572353000051547301400853197916227942996197342525312274243365673841242283
    Line 329, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/31.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10009244936 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10009244936 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 2 failures:

Test aes_stress_all_with_rand_reset has 2 failures.

0.aes_stress_all_with_rand_reset.25977702817229851420594538670322952727940215822897379859332894758090989984612
Line 1084, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 553692771 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 553692771 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.aes_stress_all_with_rand_reset.64801376733257958279478765001152426293229280525588915829190168522200259746484
Line 1645, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/5.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 3350509591 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 3350509591 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (aes_core_fi_vseq.sv:89) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_core_fi has 2 failures.
  - 37.aes_core_fi.58353481499588396109741294997557963732653945150891847529812629878875004820632
    Line 311, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/37.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10020700483 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10020700483 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 48.aes_core_fi.85699152343035395723473876217246325015733904691664044676042440135101087034971
    Line 320, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/48.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10033061068 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10033061068 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:775) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited too long to issue a reset with no outstanding accesses. has 1 failures:
- Test aes_csr_mem_rw_with_rand_reset has 1 failures.
  - 1.aes_csr_mem_rw_with_rand_reset.78034170773216913762593490584745250651897371153066476594113953850262930054474
    Line 292, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 115886706 ps: (cip_base_vseq.sv:775) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited too long to issue a reset with no outstanding accesses.
  UVM_INFO @ 115886706 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,978): Assertion AesSecCmDataRegLocalEscDataOut has failed (* cycles, starting * PS) has 1 failures:
- Test aes_alert_reset has 1 failures.
  - 2.aes_alert_reset.99288223007736485676927870774615811939587058417301132092120615918780147059487
    Line 589, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/2.aes_alert_reset/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,978): (time 9108359 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 9097942 PS)
  UVM_ERROR @   9108359 ps: (aes_core.sv:978) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut
  UVM_INFO @   9108359 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:525) [aes_alert_reset_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_fault fired unexpectedly! has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 6.aes_stress_all_with_rand_reset.15018949713642029362406676340261563915207726610059156482517848003759349274990
    Line 383, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/6.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 373294622 ps: (cip_base_vseq.sv:525) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_fault fired unexpectedly!
  UVM_INFO @ 373294622 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_reseed_vseq.sv:28) [aes_reseed_vseq] Check failed request_seen == *'b* (* [*] vs * [*]) has 1 failures:
- Test aes_stress_all has 1 failures.
  - 8.aes_stress_all.72862979655369376257922815145576682703728180663376005863839302707213517662344
    Line 405, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/8.aes_stress_all/latest/run.log
```
  UVM_FATAL @  86840352 ps: (aes_reseed_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed request_seen == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @  86840352 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:572) [csr_utils::csr_spinwait] timeout aes_reg_block.status.output_valid (addr=*) == * has 1 failures:
- Test aes_same_csr_outstanding has 1 failures.
  - 19.aes_same_csr_outstanding.34465712978649580017979451055485000664807915716260649608007813602342939096601
    Line 290, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/19.aes_same_csr_outstanding/latest/run.log
```
  UVM_FATAL @ 10026956774 ps: (csr_utils_pkg.sv:572) [csr_utils::csr_spinwait] timeout aes_reg_block.status.output_valid (addr=0xa48f5284) == 0x0
  UVM_INFO @ 10026956774 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:572) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=*) == * has 1 failures:
- Test aes_core_fi has 1 failures.
  - 64.aes_core_fi.50390829856527808567125125529583936366539116838663410937322832697142428557815
    Line 322, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/64.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10010145688 ps: (csr_utils_pkg.sv:572) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0x5ada5f84) == 0x0
  UVM_INFO @ 10010145688 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```