AES/UNMASKED Simulation Results

Sunday February 25 2024 20:02:21 UTC

GitHub Revision: `49a27e136c`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 17821327886248910358472250431024817182401150698618588470408418907520000067582

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	4.000s	59.439us	1	1	100.00
V1	smoke	aes_smoke	4.000s	56.827us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	9.000s	86.451us	5	5	100.00
V1	csr_rw	aes_csr_rw	13.000s	56.116us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	13.000s	1.692ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	16.000s	145.053us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	19.000s	307.840us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	13.000s	56.116us	20	20	100.00
		aes_csr_aliasing	16.000s	145.053us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	4.000s	56.827us	50	50	100.00
		aes_config_error	7.000s	160.575us	50	50	100.00
		aes_stress	6.000s	227.612us	50	50	100.00
V2	key_length	aes_smoke	4.000s	56.827us	50	50	100.00
		aes_config_error	7.000s	160.575us	50	50	100.00
		aes_stress	6.000s	227.612us	50	50	100.00
V2	back2back	aes_stress	6.000s	227.612us	50	50	100.00
		aes_b2b	11.000s	121.440us	50	50	100.00
V2	backpressure	aes_stress	6.000s	227.612us	50	50	100.00
V2	multi_message	aes_smoke	4.000s	56.827us	50	50	100.00
		aes_config_error	7.000s	160.575us	50	50	100.00
		aes_stress	6.000s	227.612us	50	50	100.00
		aes_alert_reset	5.000s	102.955us	48	50	96.00
V2	failure_test	aes_man_cfg_err	4.000s	71.817us	50	50	100.00
		aes_config_error	7.000s	160.575us	50	50	100.00
		aes_alert_reset	5.000s	102.955us	48	50	96.00
V2	trigger_clear_test	aes_clear	7.000s	192.683us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	5.000s	107.666us	1	1	100.00
V2	reset_recovery	aes_alert_reset	5.000s	102.955us	48	50	96.00
V2	stress	aes_stress	6.000s	227.612us	50	50	100.00
V2	sideload	aes_stress	6.000s	227.612us	50	50	100.00
		aes_sideload	5.000s	106.657us	50	50	100.00
V2	deinitialization	aes_deinit	6.000s	210.329us	50	50	100.00
V2	stress_all	aes_stress_all	41.000s	15.740ms	10	10	100.00
V2	alert_test	aes_alert_test	4.000s	174.918us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	19.000s	84.588us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	19.000s	84.588us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	9.000s	86.451us	5	5	100.00
		aes_csr_rw	13.000s	56.116us	20	20	100.00
		aes_csr_aliasing	16.000s	145.053us	5	5	100.00
		aes_same_csr_outstanding	1.000m	10.116ms	19	20	95.00
V2	tl_d_partial_access	aes_csr_hw_reset	9.000s	86.451us	5	5	100.00
		aes_csr_rw	13.000s	56.116us	20	20	100.00
		aes_csr_aliasing	16.000s	145.053us	5	5	100.00
		aes_same_csr_outstanding	1.000m	10.116ms	19	20	95.00
V2		TOTAL			498	501	99.40
V2S	reseeding	aes_reseed	6.000s	1.089ms	50	50	100.00
V2S	fault_inject	aes_fi	5.000s	106.243us	46	50	92.00
		aes_control_fi	48.000s	10.003ms	270	300	90.00
		aes_cipher_fi	46.000s	10.051ms	319	350	91.14
V2S	shadow_reg_update_error	aes_shadow_reg_errors	21.000s	133.655us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	21.000s	133.655us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	21.000s	133.655us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	21.000s	133.655us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	21.000s	138.477us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	6.000s	1.200ms	5	5	100.00
		aes_tl_intg_err	20.000s	167.818us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	20.000s	167.818us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	5.000s	102.955us	48	50	96.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	21.000s	133.655us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	4.000s	56.827us	50	50	100.00
		aes_stress	6.000s	227.612us	50	50	100.00
		aes_alert_reset	5.000s	102.955us	48	50	96.00
		aes_core_fi	22.000s	10.009ms	69	70	98.57
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	21.000s	133.655us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	4.000s	80.458us	50	50	100.00
		aes_stress	6.000s	227.612us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	6.000s	227.612us	50	50	100.00
		aes_sideload	5.000s	106.657us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	4.000s	80.458us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	4.000s	80.458us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	4.000s	80.458us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	4.000s	80.458us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	4.000s	80.458us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	6.000s	227.612us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	6.000s	227.612us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	5.000s	106.243us	46	50	92.00
V2S	sec_cm_main_fsm_redun	aes_fi	5.000s	106.243us	46	50	92.00
		aes_control_fi	48.000s	10.003ms	270	300	90.00
		aes_cipher_fi	46.000s	10.051ms	319	350	91.14
		aes_ctr_fi	4.000s	215.542us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	5.000s	106.243us	46	50	92.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	5.000s	106.243us	46	50	92.00
		aes_control_fi	48.000s	10.003ms	270	300	90.00
		aes_cipher_fi	46.000s	10.051ms	319	350	91.14
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	46.000s	10.051ms	319	350	91.14
V2S	sec_cm_ctr_fsm_sparse	aes_fi	5.000s	106.243us	46	50	92.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	5.000s	106.243us	46	50	92.00
		aes_control_fi	48.000s	10.003ms	270	300	90.00
		aes_ctr_fi	4.000s	215.542us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	5.000s	106.243us	46	50	92.00
		aes_control_fi	48.000s	10.003ms	270	300	90.00
		aes_cipher_fi	46.000s	10.051ms	319	350	91.14
		aes_ctr_fi	4.000s	215.542us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	5.000s	102.955us	48	50	96.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	5.000s	106.243us	46	50	92.00
		aes_control_fi	48.000s	10.003ms	270	300	90.00
		aes_cipher_fi	46.000s	10.051ms	319	350	91.14
		aes_ctr_fi	4.000s	215.542us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	5.000s	106.243us	46	50	92.00
		aes_control_fi	48.000s	10.003ms	270	300	90.00
		aes_cipher_fi	46.000s	10.051ms	319	350	91.14
		aes_ctr_fi	4.000s	215.542us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	5.000s	106.243us	46	50	92.00
		aes_control_fi	48.000s	10.003ms	270	300	90.00
		aes_ctr_fi	4.000s	215.542us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	5.000s	106.243us	46	50	92.00
		aes_control_fi	48.000s	10.003ms	270	300	90.00
		aes_cipher_fi	46.000s	10.051ms	319	350	91.14
V2S		TOTAL			919	985	93.30
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	4.467m	5.044ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1523	1602	95.07

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	11	84.62
V2S	11	11	7	63.64
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.17	97.40	94.16	98.77	93.96	97.72	91.11	98.85	95.61

Failure Buckets

Job aes_unmasked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 34 failures:
- Test aes_cipher_fi has 15 failures.
  - 3.aes_cipher_fi.21139747398813469262864747384064175293493682629689111895181722148635378433199
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/3.aes_cipher_fi/latest/run.log
```
  Job ID: smart:dad1fcaf-c1ee-4a38-8e02-599375310e52
```
  - 50.aes_cipher_fi.83147642283364654967269694808806889467862558886826200029038762611584814976478
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/50.aes_cipher_fi/latest/run.log
```
  Job ID: smart:21d6a5c8-d10b-45c7-8dca-420101b6b01d
```
  - ... and 13 more failures.
- Test aes_control_fi has 19 failures.
  - 39.aes_control_fi.56273927706260823721819126995802752374519193486799678277046225354915467590866
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/39.aes_control_fi/latest/run.log
```
  Job ID: smart:7f2a4499-7441-4518-8264-d9d761033fa0
```
  - 42.aes_control_fi.16878647978519025563594210977388972559479145710599115143302003308745181219248
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/42.aes_control_fi/latest/run.log
```
  Job ID: smart:ac0c0190-8426-4ad9-8bca-9c16b171049f
```
  - ... and 17 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 15 failures:
- Test aes_cipher_fi has 15 failures.
  - 14.aes_cipher_fi.7982532347367882317409681040283684573063360071135505164528300677110400186103
    Line 324, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/14.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10021917462 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10021917462 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 99.aes_cipher_fi.85108775728000442853509707257627099137855422899378897080568379136036970176754
    Line 325, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/99.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10009533929 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10009533929 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 13 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 11 failures:
- Test aes_control_fi has 11 failures.
  - 1.aes_control_fi.100431116593530212821176788182388413001391516286874418702996684543806232944587
    Line 312, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10002600207 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10002600207 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 35.aes_control_fi.31338902330297771520301886095260279569716842073411600347354626552106703031715
    Line 321, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/35.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10012210599 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10012210599 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 9 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 6 failures:

Test aes_stress_all_with_rand_reset has 6 failures.

0.aes_stress_all_with_rand_reset.24127629069171756263038015512940384410888249750363349068775879541742901757293
Line 1018, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 617722921 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 617722921 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.86997460141953051771047639244520756841361825726621000941604840465220666859857
Line 1696, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 3545778808 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 3545778808 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 2 failures:

Test aes_stress_all_with_rand_reset has 2 failures.

3.aes_stress_all_with_rand_reset.14602752424911645619401399082926506706430321212497984596847403484256733891842
Line 1553, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 4969878893 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 4969878893 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

8.aes_stress_all_with_rand_reset.30122973934803703910921873396055768395453549741116580599778805704304025378449
Line 1030, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/8.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 926629482 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 926629482 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,978): Assertion AesSecCmDataRegLocalEscDataOut has failed (* cycles, starting * PS) has 2 failures:

Test aes_alert_reset has 2 failures.

12.aes_alert_reset.21875667364352962337210103577416515797932145983143939349114984106706822166773
Line 1224, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/12.aes_alert_reset/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,978): (time 105845183 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 105754274 PS)
  UVM_ERROR @ 105845183 ps: (aes_core.sv:978) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut
  UVM_INFO @ 105845183 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

33.aes_alert_reset.102372157983887345108543690862678732077743369611184300148417494900180849969629
Line 812, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/33.aes_alert_reset/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,978): (time 10078534 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 10038534 PS)
  UVM_ERROR @  10078534 ps: (aes_core.sv:978) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut
  UVM_INFO @  10078534 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (aes_fi_vseq.sv:69) virtual_sequencer [aes_fi_vseq] Was Able to finish without clearing reset has 2 failures:

Test aes_fi has 2 failures.

25.aes_fi.78324342159072973711630203943618410147644312875973525462787111356558193895859
Line 4567, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/25.aes_fi/latest/run.log

  UVM_FATAL @  50506951 ps: (aes_fi_vseq.sv:69) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.aes_fi_vseq] Was Able to finish without clearing reset
  UVM_INFO @  50506951 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

48.aes_fi.55179819784902421767942196870910482080893914544176935852975369899666366062681
Line 2478, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/48.aes_fi/latest/run.log

  UVM_FATAL @  11458922 ps: (aes_fi_vseq.sv:69) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.aes_fi_vseq] Was Able to finish without clearing reset
  UVM_INFO @  11458922 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,984): Assertion AesSecCmDataRegLocalEscIv has failed (* cycles, starting * PS) has 2 failures:

Test aes_fi has 2 failures.

26.aes_fi.79195772311935036522740672917955043062127512847471097995085750237272835459532
Line 3583, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/26.aes_fi/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,984): (time 24469549 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 24443908 PS)
  UVM_ERROR @  24469549 ps: (aes_core.sv:984) [ASSERT FAILED] AesSecCmDataRegLocalEscIv
  UVM_INFO @  24469549 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

28.aes_fi.82996437834142556251066839570008947547867683902337603470671082349581361683079
Line 689, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/28.aes_fi/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,984): (time 14462831 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 14440104 PS)
  UVM_ERROR @  14462831 ps: (aes_core.sv:984) [ASSERT FAILED] AesSecCmDataRegLocalEscIv
  UVM_INFO @  14462831 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_vseq.sv:525) [aes_alert_reset_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_fault fired unexpectedly! has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 4.aes_stress_all_with_rand_reset.88410353609976344229424046628569023943511371694503741798440990770178014691734
    Line 318, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/4.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 117432913 ps: (cip_base_vseq.sv:525) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_fault fired unexpectedly!
  UVM_INFO @ 117432913 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:775) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited too long to issue a reset with no outstanding accesses. has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 6.aes_stress_all_with_rand_reset.35361613048413003824948666118877813978285996869161710883146928546966274600103
    Line 682, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/6.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 5044426401 ps: (cip_base_vseq.sv:775) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited too long to issue a reset with no outstanding accesses.
  UVM_INFO @ 5044426401 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 16.aes_core_fi.80850775025012973685557282654345689606039154781890576027516760932900945559456
    Line 317, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/16.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10008675063 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10008675063 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:572) [csr_utils::csr_spinwait] timeout aes_reg_block.status.output_valid (addr=*) == * has 1 failures:
- Test aes_same_csr_outstanding has 1 failures.
  - 18.aes_same_csr_outstanding.47323886251187996077112113858697144433417382548355946712472734243007876466009
    Line 308, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/18.aes_same_csr_outstanding/latest/run.log
```
  UVM_FATAL @ 10116095625 ps: (csr_utils_pkg.sv:572) [csr_utils::csr_spinwait] timeout aes_reg_block.status.output_valid (addr=0x1deb2784) == 0x0
  UVM_INFO @ 10116095625 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 1 failures:
- Test aes_cipher_fi has 1 failures.
  - 256.aes_cipher_fi.51269492939864072519842426620401690725117256959271433049931296079737555272605
    Line 332, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/256.aes_cipher_fi/latest/run.log
```
  UVM_ERROR @  20503556 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_tl_agent_aes_reg_block.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_tl_agent_aes_reg_block.sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @  20503556 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```