AES/UNMASKED Simulation Results

Wednesday February 28 2024 23:53:28 UTC

GitHub Revision: `32ed2c4230`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 10708067410766204292161266966839433462058030635847883045650346145926493105783

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	2.000s	60.113us	1	1	100.00
V1	smoke	aes_smoke	4.000s	98.453us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	59.319us	5	5	100.00
V1	csr_rw	aes_csr_rw	3.000s	61.362us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	8.000s	325.322us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	132.686us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	7.000s	247.717us	19	20	95.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	3.000s	61.362us	20	20	100.00
		aes_csr_aliasing	5.000s	132.686us	5	5	100.00
V1		TOTAL			105	106	99.06
V2	algorithm	aes_smoke	4.000s	98.453us	50	50	100.00
		aes_config_error	11.000s	456.658us	50	50	100.00
		aes_stress	5.000s	105.782us	50	50	100.00
V2	key_length	aes_smoke	4.000s	98.453us	50	50	100.00
		aes_config_error	11.000s	456.658us	50	50	100.00
		aes_stress	5.000s	105.782us	50	50	100.00
V2	back2back	aes_stress	5.000s	105.782us	50	50	100.00
		aes_b2b	10.000s	133.049us	50	50	100.00
V2	backpressure	aes_stress	5.000s	105.782us	50	50	100.00
V2	multi_message	aes_smoke	4.000s	98.453us	50	50	100.00
		aes_config_error	11.000s	456.658us	50	50	100.00
		aes_stress	5.000s	105.782us	50	50	100.00
		aes_alert_reset	5.000s	108.776us	50	50	100.00
V2	failure_test	aes_man_cfg_err	4.000s	79.718us	50	50	100.00
		aes_config_error	11.000s	456.658us	50	50	100.00
		aes_alert_reset	5.000s	108.776us	50	50	100.00
V2	trigger_clear_test	aes_clear	6.000s	221.031us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	6.000s	136.616us	1	1	100.00
V2	reset_recovery	aes_alert_reset	5.000s	108.776us	50	50	100.00
V2	stress	aes_stress	5.000s	105.782us	50	50	100.00
V2	sideload	aes_stress	5.000s	105.782us	50	50	100.00
		aes_sideload	7.000s	214.210us	50	50	100.00
V2	deinitialization	aes_deinit	5.000s	95.440us	50	50	100.00
V2	stress_all	aes_stress_all	34.000s	1.480ms	10	10	100.00
V2	alert_test	aes_alert_test	4.000s	54.961us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	5.000s	93.488us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	5.000s	93.488us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	59.319us	5	5	100.00
		aes_csr_rw	3.000s	61.362us	20	20	100.00
		aes_csr_aliasing	5.000s	132.686us	5	5	100.00
		aes_same_csr_outstanding	4.000s	117.692us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	59.319us	5	5	100.00
		aes_csr_rw	3.000s	61.362us	20	20	100.00
		aes_csr_aliasing	5.000s	132.686us	5	5	100.00
		aes_same_csr_outstanding	4.000s	117.692us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	7.000s	1.359ms	50	50	100.00
V2S	fault_inject	aes_fi	6.000s	245.412us	50	50	100.00
		aes_control_fi	50.000s	37.528ms	273	300	91.00
		aes_cipher_fi	47.000s	47.752ms	321	350	91.71
V2S	shadow_reg_update_error	aes_shadow_reg_errors	3.000s	96.710us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	3.000s	96.710us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	3.000s	96.710us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	3.000s	96.710us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	4.000s	275.893us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	6.000s	586.442us	5	5	100.00
		aes_tl_intg_err	5.000s	143.014us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	5.000s	143.014us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	5.000s	108.776us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	3.000s	96.710us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	4.000s	98.453us	50	50	100.00
		aes_stress	5.000s	105.782us	50	50	100.00
		aes_alert_reset	5.000s	108.776us	50	50	100.00
		aes_core_fi	3.567m	10.022ms	65	70	92.86
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	3.000s	96.710us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	4.000s	61.949us	50	50	100.00
		aes_stress	5.000s	105.782us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	5.000s	105.782us	50	50	100.00
		aes_sideload	7.000s	214.210us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	4.000s	61.949us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	4.000s	61.949us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	4.000s	61.949us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	4.000s	61.949us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	4.000s	61.949us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	5.000s	105.782us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	5.000s	105.782us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	6.000s	245.412us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	6.000s	245.412us	50	50	100.00
		aes_control_fi	50.000s	37.528ms	273	300	91.00
		aes_cipher_fi	47.000s	47.752ms	321	350	91.71
		aes_ctr_fi	4.000s	78.274us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	6.000s	245.412us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	6.000s	245.412us	50	50	100.00
		aes_control_fi	50.000s	37.528ms	273	300	91.00
		aes_cipher_fi	47.000s	47.752ms	321	350	91.71
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	47.000s	47.752ms	321	350	91.71
V2S	sec_cm_ctr_fsm_sparse	aes_fi	6.000s	245.412us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	6.000s	245.412us	50	50	100.00
		aes_control_fi	50.000s	37.528ms	273	300	91.00
		aes_ctr_fi	4.000s	78.274us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	6.000s	245.412us	50	50	100.00
		aes_control_fi	50.000s	37.528ms	273	300	91.00
		aes_cipher_fi	47.000s	47.752ms	321	350	91.71
		aes_ctr_fi	4.000s	78.274us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	5.000s	108.776us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	6.000s	245.412us	50	50	100.00
		aes_control_fi	50.000s	37.528ms	273	300	91.00
		aes_cipher_fi	47.000s	47.752ms	321	350	91.71
		aes_ctr_fi	4.000s	78.274us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	6.000s	245.412us	50	50	100.00
		aes_control_fi	50.000s	37.528ms	273	300	91.00
		aes_cipher_fi	47.000s	47.752ms	321	350	91.71
		aes_ctr_fi	4.000s	78.274us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	6.000s	245.412us	50	50	100.00
		aes_control_fi	50.000s	37.528ms	273	300	91.00
		aes_ctr_fi	4.000s	78.274us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	6.000s	245.412us	50	50	100.00
		aes_control_fi	50.000s	37.528ms	273	300	91.00
		aes_cipher_fi	47.000s	47.752ms	321	350	91.71
V2S		TOTAL			924	985	93.81
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	3.833m	39.570ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1530	1602	95.51

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	6	85.71
V2	13	13	13	100.00
V2S	11	11	8	72.73
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.16	97.46	94.24	98.81	93.70	97.64	91.11	98.85	95.61

Failure Buckets

Job aes_unmasked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 33 failures:
- Test aes_control_fi has 17 failures.
  - 3.aes_control_fi.56658981787939511509657645871159181951058554471517340769325112726540710841806
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/3.aes_control_fi/latest/run.log
```
  Job ID: smart:9949a631-16c9-4225-8ef5-a7b1a4ded354
```
  - 42.aes_control_fi.29420618707694511880768810080675710180343659112884203245514773956033183176348
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/42.aes_control_fi/latest/run.log
```
  Job ID: smart:e14074e1-3134-4d30-a88d-8520400ff9e1
```
  - ... and 15 more failures.
- Test aes_cipher_fi has 16 failures.
  - 7.aes_cipher_fi.15180671594192128212706211554802472704750282065088013009861887537235311025454
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/7.aes_cipher_fi/latest/run.log
```
  Job ID: smart:ee4f8513-f85b-420a-823b-1207196d890a
```
  - 8.aes_cipher_fi.104081795511898194964155497846868375666780940301372487971573759989553184954231
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/8.aes_cipher_fi/latest/run.log
```
  Job ID: smart:2f49aa5e-9d0c-4ba7-80de-dde62fcc0b8f
```
  - ... and 14 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 13 failures:
- Test aes_cipher_fi has 13 failures.
  - 17.aes_cipher_fi.40382184279297844727066983471558942895737848783557686193025558078961574437852
    Line 320, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/17.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10006345722 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006345722 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 46.aes_cipher_fi.28748657426985562723359721770904499661133738484309964699785121773749163178152
    Line 318, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/46.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10013507170 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10013507170 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 11 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 10 failures:
- Test aes_control_fi has 10 failures.
  - 7.aes_control_fi.66016642464849835332730422351455882668409110420509629101420163808338942266226
    Line 324, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/7.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10023059115 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10023059115 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 43.aes_control_fi.47185857959920695914928840412581219415285127366960452899456209454004932305802
    Line 324, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/43.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10034985810 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10034985810 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 8 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 5 failures:

Test aes_stress_all_with_rand_reset has 5 failures.

0.aes_stress_all_with_rand_reset.114580612405722112711245500315785375633073818866730141131922476975148692209583
Line 1947, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 492775792 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 492775792 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.98424061508043105662314469055879111849393052928187409787938249269746417952072
Line 1666, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2839374871 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 2839374871 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 5 failures:

Test aes_stress_all_with_rand_reset has 5 failures.

3.aes_stress_all_with_rand_reset.388795752066008387448070861411188953316437505633952749186971176983966290283
Line 505, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 39569678571 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 39569678571 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.aes_stress_all_with_rand_reset.46891486491123509685712349483582090805456465685707929615305577197779471845585
Line 1351, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/4.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 659948748 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 659948748 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 3 failures:
- Test aes_core_fi has 3 failures.
  - 17.aes_core_fi.45987557429168434012546643419372244969429651742014125605809381476393274335152
    Line 324, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/17.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10006563361 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006563361 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 39.aes_core_fi.95500260758101083503268709671377658579379408256321660744886929903580998357508
    Line 322, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/39.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10014281083 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10014281083 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:789) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test aes_csr_mem_rw_with_rand_reset has 1 failures.
  - 0.aes_csr_mem_rw_with_rand_reset.50906607336431289312908993327836891078034818784569329015481907064473220920280
    Line 292, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 247717495 ps: (cip_base_vseq.sv:789) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 247717495 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:89) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 27.aes_core_fi.79673916300345003445028171152023695991985388366063156154318275858797778443730
    Line 319, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/27.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10020467095 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10020467095 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:572) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=*) == * has 1 failures:
- Test aes_core_fi has 1 failures.
  - 30.aes_core_fi.29237166575085713245435081615522432599931591544048449757381598590968543462958
    Line 314, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/30.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10021972929 ps: (csr_utils_pkg.sv:572) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0x1c73b584) == 0x0
  UVM_INFO @ 10021972929 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```