AES/UNMASKED Simulation Results

Sunday March 17 2024 19:02:52 UTC

GitHub Revision: `c187a82ee8`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 28440605375541353837496064678278045899395893237469128852560697715229879921060

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	2.000s	87.522us	1	1	100.00
V1	smoke	aes_smoke	13.000s	84.786us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	371.536us	5	5	100.00
V1	csr_rw	aes_csr_rw	3.000s	51.510us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	10.000s	374.823us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	251.330us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	4.000s	65.335us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	3.000s	51.510us	20	20	100.00
		aes_csr_aliasing	5.000s	251.330us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	13.000s	84.786us	50	50	100.00
		aes_config_error	8.000s	106.616us	50	50	100.00
		aes_stress	13.000s	99.622us	50	50	100.00
V2	key_length	aes_smoke	13.000s	84.786us	50	50	100.00
		aes_config_error	8.000s	106.616us	50	50	100.00
		aes_stress	13.000s	99.622us	50	50	100.00
V2	back2back	aes_stress	13.000s	99.622us	50	50	100.00
		aes_b2b	11.000s	148.875us	50	50	100.00
V2	backpressure	aes_stress	13.000s	99.622us	50	50	100.00
V2	multi_message	aes_smoke	13.000s	84.786us	50	50	100.00
		aes_config_error	8.000s	106.616us	50	50	100.00
		aes_stress	13.000s	99.622us	50	50	100.00
		aes_alert_reset	12.000s	70.437us	50	50	100.00
V2	failure_test	aes_man_cfg_err	13.000s	170.900us	50	50	100.00
		aes_config_error	8.000s	106.616us	50	50	100.00
		aes_alert_reset	12.000s	70.437us	50	50	100.00
V2	trigger_clear_test	aes_clear	9.000s	139.334us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	7.000s	195.311us	1	1	100.00
V2	reset_recovery	aes_alert_reset	12.000s	70.437us	50	50	100.00
V2	stress	aes_stress	13.000s	99.622us	50	50	100.00
V2	sideload	aes_stress	13.000s	99.622us	50	50	100.00
		aes_sideload	8.000s	83.271us	50	50	100.00
V2	deinitialization	aes_deinit	14.000s	247.702us	50	50	100.00
V2	stress_all	aes_stress_all	36.000s	7.797ms	10	10	100.00
V2	alert_test	aes_alert_test	8.000s	86.377us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	7.000s	247.869us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	7.000s	247.869us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	371.536us	5	5	100.00
		aes_csr_rw	3.000s	51.510us	20	20	100.00
		aes_csr_aliasing	5.000s	251.330us	5	5	100.00
		aes_same_csr_outstanding	5.000s	1.044ms	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	371.536us	5	5	100.00
		aes_csr_rw	3.000s	51.510us	20	20	100.00
		aes_csr_aliasing	5.000s	251.330us	5	5	100.00
		aes_same_csr_outstanding	5.000s	1.044ms	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	9.000s	97.223us	50	50	100.00
V2S	fault_inject	aes_fi	9.000s	138.384us	47	50	94.00
		aes_control_fi	48.000s	16.443ms	282	300	94.00
		aes_cipher_fi	53.000s	200.000ms	317	350	90.57
V2S	shadow_reg_update_error	aes_shadow_reg_errors	3.000s	279.101us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	3.000s	279.101us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	3.000s	279.101us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	3.000s	279.101us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	4.000s	160.638us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	6.000s	651.859us	5	5	100.00
		aes_tl_intg_err	6.000s	814.266us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	6.000s	814.266us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	12.000s	70.437us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	3.000s	279.101us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	13.000s	84.786us	50	50	100.00
		aes_stress	13.000s	99.622us	50	50	100.00
		aes_alert_reset	12.000s	70.437us	50	50	100.00
		aes_core_fi	31.000s	10.022ms	66	70	94.29
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	3.000s	279.101us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	4.000s	90.213us	50	50	100.00
		aes_stress	13.000s	99.622us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	13.000s	99.622us	50	50	100.00
		aes_sideload	8.000s	83.271us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	4.000s	90.213us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	4.000s	90.213us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	4.000s	90.213us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	4.000s	90.213us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	4.000s	90.213us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	13.000s	99.622us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	13.000s	99.622us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	9.000s	138.384us	47	50	94.00
V2S	sec_cm_main_fsm_redun	aes_fi	9.000s	138.384us	47	50	94.00
		aes_control_fi	48.000s	16.443ms	282	300	94.00
		aes_cipher_fi	53.000s	200.000ms	317	350	90.57
		aes_ctr_fi	7.000s	107.692us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	9.000s	138.384us	47	50	94.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	9.000s	138.384us	47	50	94.00
		aes_control_fi	48.000s	16.443ms	282	300	94.00
		aes_cipher_fi	53.000s	200.000ms	317	350	90.57
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	53.000s	200.000ms	317	350	90.57
V2S	sec_cm_ctr_fsm_sparse	aes_fi	9.000s	138.384us	47	50	94.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	9.000s	138.384us	47	50	94.00
		aes_control_fi	48.000s	16.443ms	282	300	94.00
		aes_ctr_fi	7.000s	107.692us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	9.000s	138.384us	47	50	94.00
		aes_control_fi	48.000s	16.443ms	282	300	94.00
		aes_cipher_fi	53.000s	200.000ms	317	350	90.57
		aes_ctr_fi	7.000s	107.692us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	12.000s	70.437us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	9.000s	138.384us	47	50	94.00
		aes_control_fi	48.000s	16.443ms	282	300	94.00
		aes_cipher_fi	53.000s	200.000ms	317	350	90.57
		aes_ctr_fi	7.000s	107.692us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	9.000s	138.384us	47	50	94.00
		aes_control_fi	48.000s	16.443ms	282	300	94.00
		aes_cipher_fi	53.000s	200.000ms	317	350	90.57
		aes_ctr_fi	7.000s	107.692us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	9.000s	138.384us	47	50	94.00
		aes_control_fi	48.000s	16.443ms	282	300	94.00
		aes_ctr_fi	7.000s	107.692us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	9.000s	138.384us	47	50	94.00
		aes_control_fi	48.000s	16.443ms	282	300	94.00
		aes_cipher_fi	53.000s	200.000ms	317	350	90.57
V2S		TOTAL			927	985	94.11
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	4.900m	20.592ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1534	1602	95.76

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	13	100.00
V2S	11	11	7	63.64
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.20	97.42	94.17	98.87	93.82	97.64	93.33	98.66	96.01

Failure Buckets

Job aes_unmasked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 35 failures:
- Test aes_cipher_fi has 24 failures.
  - 0.aes_cipher_fi.1134072998516648759776920806974898786636902601591192942767564462512319047832
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_cipher_fi/latest/run.log
```
  Job ID: smart:413df543-d7d6-4387-ad50-9b50c19462dc
```
  - 18.aes_cipher_fi.61364431621998468417770635107929187571684054718247547734772036148699493138113
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/18.aes_cipher_fi/latest/run.log
```
  Job ID: smart:951e1a76-0ff5-4714-aadf-2238d392b16b
```
  - ... and 22 more failures.
- Test aes_control_fi has 11 failures.
  - 20.aes_control_fi.107119384517455091682781754170033505390805379904595056230627230156254591718063
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/20.aes_control_fi/latest/run.log
```
  Job ID: smart:951d5090-d725-4d03-a93e-a7ec89585dfb
```
  - 37.aes_control_fi.67896002418721257120705681504504991368725217475749981034571001399766673297009
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/37.aes_control_fi/latest/run.log
```
  Job ID: smart:0d61a3bf-87ec-4397-a0c5-ceba46ed19bc
```
  - ... and 9 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 8 failures:
- Test aes_cipher_fi has 8 failures.
  - 28.aes_cipher_fi.33051571121548418083489053444573423143732152902190007327169927466076174330809
    Line 314, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/28.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10002646499 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10002646499 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 65.aes_cipher_fi.95675896088191926725284691390457961045616263992650428699517604543820145661814
    Line 316, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/65.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10005446078 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10005446078 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 7 failures:

Test aes_stress_all_with_rand_reset has 7 failures.

0.aes_stress_all_with_rand_reset.89376205515504105217490988764631363104423466884310205600868037755030784069469
Line 686, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 716939796 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 716939796 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.aes_stress_all_with_rand_reset.74061879358672015690669687687440311211012290917319552197608704089413245680898
Line 531, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 20591985989 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 20591985989 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 7 failures:
- Test aes_control_fi has 7 failures.
  - 2.aes_control_fi.102297095563230155507143262647029768180763607039366633682445620282514539087594
    Line 326, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/2.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10010066154 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10010066154 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 32.aes_control_fi.47056184840725406011932795460982898179392347087098667704277099753938704266230
    Line 326, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/32.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10021476533 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10021476533 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 3 failures:
- Test aes_core_fi has 3 failures.
  - 14.aes_core_fi.96735077635592697397089735398612736153988001801958771040063619130169910585388
    Line 323, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/14.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10028500946 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10028500946 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 34.aes_core_fi.45368633135366643794700796639361506777417206123924954452664154430879660880972
    Line 323, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/34.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10007445075 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10007445075 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 2 failures:

Test aes_stress_all_with_rand_reset has 2 failures.

2.aes_stress_all_with_rand_reset.11685328386345289382006745066324088694750228510000271000081224689690996368827
Line 933, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 4178097172 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 4178097172 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.aes_stress_all_with_rand_reset.1657424786293875035008682377985765220606197982770100749911008569342772870694
Line 1115, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/4.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 277323344 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 277323344 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,987): Assertion AesSecCmDataRegLocalEscDataOut has failed (* cycles, starting * PS) has 2 failures:

Test aes_fi has 2 failures.

11.aes_fi.104833397649965028517592353033174514022295422057446971670884973715100467466101
Line 2276, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/11.aes_fi/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,987): (time 9116992 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 9106683 PS)
        ($past(iv_q) != $past(state_done_transposed, 2) ^ $past(data_in_prev_q, 2)))
                                                                                   |
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,993): (time 9116992 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 9106683 PS)
  UVM_ERROR @   9116992 ps: (aes_core.sv:987) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut

14.aes_fi.114223043441518164429232778667454965660095472527771283855934034059828967924066
Line 1838, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/14.aes_fi/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,987): (time 11512300 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 11491467 PS)
  UVM_ERROR @  11512300 ps: (aes_core.sv:987) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut
  UVM_INFO @  11512300 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_vseq.sv:555) [aes_alert_reset_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_fault fired unexpectedly! has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 1.aes_stress_all_with_rand_reset.62993765716085975747874255772320893350294919198426046460707405527174757934889
    Line 321, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  50175647 ps: (cip_base_vseq.sv:555) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_fault fired unexpectedly!
  UVM_INFO @  50175647 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,993): Assertion AesSecCmDataRegLocalEscIv has failed (* cycles, starting * PS) has 1 failures:
- Test aes_fi has 1 failures.
  - 6.aes_fi.67692241718459306173401300422134219734652196949870741922301386679958927114751
    Line 1103, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/6.aes_fi/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,993): (time 38176496 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 38134829 PS)
  UVM_ERROR @  38176496 ps: (aes_core.sv:993) [ASSERT FAILED] AesSecCmDataRegLocalEscIv
  UVM_INFO @  38176496 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:89) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 18.aes_core_fi.109732043202582111901248045664970436289532823729488240662546786764996259955806
    Line 315, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/18.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10021505548 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10021505548 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test aes_cipher_fi has 1 failures.
  - 248.aes_cipher_fi.18770536112471777798452168769143878875833089311969878533786901125523999626574
    Line 324, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/248.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```