AES/UNMASKED Simulation Results

Sunday March 03 2024 20:02:47 UTC

GitHub Revision: `0cdf265eaa`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 82530437672810453765703374940713112405319051694331588453064008042331386550559

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	5.000s	107.475us	1	1	100.00
V1	smoke	aes_smoke	14.000s	79.671us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	67.849us	5	5	100.00
V1	csr_rw	aes_csr_rw	3.000s	94.790us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	11.000s	3.328ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	259.975us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	7.000s	111.545us	19	20	95.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	3.000s	94.790us	20	20	100.00
		aes_csr_aliasing	5.000s	259.975us	5	5	100.00
V1		TOTAL			105	106	99.06
V2	algorithm	aes_smoke	14.000s	79.671us	50	50	100.00
		aes_config_error	14.000s	99.898us	50	50	100.00
		aes_stress	14.000s	160.326us	50	50	100.00
V2	key_length	aes_smoke	14.000s	79.671us	50	50	100.00
		aes_config_error	14.000s	99.898us	50	50	100.00
		aes_stress	14.000s	160.326us	50	50	100.00
V2	back2back	aes_stress	14.000s	160.326us	50	50	100.00
		aes_b2b	15.000s	115.169us	50	50	100.00
V2	backpressure	aes_stress	14.000s	160.326us	50	50	100.00
V2	multi_message	aes_smoke	14.000s	79.671us	50	50	100.00
		aes_config_error	14.000s	99.898us	50	50	100.00
		aes_stress	14.000s	160.326us	50	50	100.00
		aes_alert_reset	13.000s	194.379us	50	50	100.00
V2	failure_test	aes_man_cfg_err	13.000s	71.658us	50	50	100.00
		aes_config_error	14.000s	99.898us	50	50	100.00
		aes_alert_reset	13.000s	194.379us	50	50	100.00
V2	trigger_clear_test	aes_clear	15.000s	81.940us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	7.000s	263.508us	1	1	100.00
V2	reset_recovery	aes_alert_reset	13.000s	194.379us	50	50	100.00
V2	stress	aes_stress	14.000s	160.326us	50	50	100.00
V2	sideload	aes_stress	14.000s	160.326us	50	50	100.00
		aes_sideload	14.000s	82.651us	50	50	100.00
V2	deinitialization	aes_deinit	14.000s	105.022us	50	50	100.00
V2	stress_all	aes_stress_all	28.000s	1.811ms	10	10	100.00
V2	alert_test	aes_alert_test	17.000s	60.095us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	7.000s	455.043us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	7.000s	455.043us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	67.849us	5	5	100.00
		aes_csr_rw	3.000s	94.790us	20	20	100.00
		aes_csr_aliasing	5.000s	259.975us	5	5	100.00
		aes_same_csr_outstanding	4.000s	132.688us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	67.849us	5	5	100.00
		aes_csr_rw	3.000s	94.790us	20	20	100.00
		aes_csr_aliasing	5.000s	259.975us	5	5	100.00
		aes_same_csr_outstanding	4.000s	132.688us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	19.000s	60.660us	50	50	100.00
V2S	fault_inject	aes_fi	13.000s	66.939us	50	50	100.00
		aes_control_fi	48.000s	16.442ms	270	300	90.00
		aes_cipher_fi	50.000s	31.530ms	322	350	92.00
V2S	shadow_reg_update_error	aes_shadow_reg_errors	3.000s	63.403us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	3.000s	63.403us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	3.000s	63.403us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	3.000s	63.403us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	4.000s	119.379us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	11.000s	457.828us	5	5	100.00
		aes_tl_intg_err	6.000s	1.174ms	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	6.000s	1.174ms	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	13.000s	194.379us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	3.000s	63.403us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	14.000s	79.671us	50	50	100.00
		aes_stress	14.000s	160.326us	50	50	100.00
		aes_alert_reset	13.000s	194.379us	50	50	100.00
		aes_core_fi	6.300m	10.006ms	65	70	92.86
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	3.000s	63.403us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	8.000s	93.058us	49	50	98.00
		aes_stress	14.000s	160.326us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	14.000s	160.326us	50	50	100.00
		aes_sideload	14.000s	82.651us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	8.000s	93.058us	49	50	98.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	8.000s	93.058us	49	50	98.00
V2S	sec_cm_key_sec_wipe	aes_readability	8.000s	93.058us	49	50	98.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	8.000s	93.058us	49	50	98.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	8.000s	93.058us	49	50	98.00
V2S	sec_cm_data_reg_key_sca	aes_stress	14.000s	160.326us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	14.000s	160.326us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	13.000s	66.939us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	13.000s	66.939us	50	50	100.00
		aes_control_fi	48.000s	16.442ms	270	300	90.00
		aes_cipher_fi	50.000s	31.530ms	322	350	92.00
		aes_ctr_fi	14.000s	100.213us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	13.000s	66.939us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	13.000s	66.939us	50	50	100.00
		aes_control_fi	48.000s	16.442ms	270	300	90.00
		aes_cipher_fi	50.000s	31.530ms	322	350	92.00
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	50.000s	31.530ms	322	350	92.00
V2S	sec_cm_ctr_fsm_sparse	aes_fi	13.000s	66.939us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	13.000s	66.939us	50	50	100.00
		aes_control_fi	48.000s	16.442ms	270	300	90.00
		aes_ctr_fi	14.000s	100.213us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	13.000s	66.939us	50	50	100.00
		aes_control_fi	48.000s	16.442ms	270	300	90.00
		aes_cipher_fi	50.000s	31.530ms	322	350	92.00
		aes_ctr_fi	14.000s	100.213us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	13.000s	194.379us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	13.000s	66.939us	50	50	100.00
		aes_control_fi	48.000s	16.442ms	270	300	90.00
		aes_cipher_fi	50.000s	31.530ms	322	350	92.00
		aes_ctr_fi	14.000s	100.213us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	13.000s	66.939us	50	50	100.00
		aes_control_fi	48.000s	16.442ms	270	300	90.00
		aes_cipher_fi	50.000s	31.530ms	322	350	92.00
		aes_ctr_fi	14.000s	100.213us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	13.000s	66.939us	50	50	100.00
		aes_control_fi	48.000s	16.442ms	270	300	90.00
		aes_ctr_fi	14.000s	100.213us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	13.000s	66.939us	50	50	100.00
		aes_control_fi	48.000s	16.442ms	270	300	90.00
		aes_cipher_fi	50.000s	31.530ms	322	350	92.00
V2S		TOTAL			921	985	93.50
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	3.200m	8.777ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1527	1602	95.32

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	6	85.71
V2	13	13	13	100.00
V2S	11	11	7	63.64
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.17	97.42	94.16	98.81	93.79	97.72	90.37	98.85	96.41

Failure Buckets

Job aes_unmasked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 38 failures:
- Test aes_control_fi has 20 failures.
  - 30.aes_control_fi.114453248291347861066189400743931825727971895845613626200498223329709035588912
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/30.aes_control_fi/latest/run.log
```
  Job ID: smart:82b0332f-6c79-45fd-a658-d5eb64c01af6
```
  - 43.aes_control_fi.112649456145362872659855162121468123044906070624308955159818761789391020446244
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/43.aes_control_fi/latest/run.log
```
  Job ID: smart:259e3f96-f737-4fef-a551-af743c714888
```
  - ... and 18 more failures.
- Test aes_cipher_fi has 18 failures.
  - 38.aes_cipher_fi.101114877611165353233812775442656328448493723969588952049472358552195071424053
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/38.aes_cipher_fi/latest/run.log
```
  Job ID: smart:9daaaa78-0d3c-49b1-9bb0-46348f4eadf4
```
  - 59.aes_cipher_fi.50652233771612204461091377599779410552125996823275466180307661618366264514011
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/59.aes_cipher_fi/latest/run.log
```
  Job ID: smart:db1ae993-7347-4103-8123-1f815af4c632
```
  - ... and 16 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 10 failures:
- Test aes_control_fi has 10 failures.
  - 6.aes_control_fi.69370996059411060469095374443228698308622242059934174229985110470136210162040
    Line 329, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/6.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10010639187 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10010639187 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 23.aes_control_fi.76133031597784669908331879275046247659852730538579718761250289320152943242521
    Line 320, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/23.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10027854165 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10027854165 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 8 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 10 failures:
- Test aes_cipher_fi has 10 failures.
  - 18.aes_cipher_fi.40668144972846780093920293240890908036305736079421651014640820519280949592407
    Line 324, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/18.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10007299399 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10007299399 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 21.aes_cipher_fi.76794251836084123554711076724098729929796779926575895820929996039904819405993
    Line 320, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/21.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10008429834 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10008429834 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 8 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 6 failures:

Test aes_stress_all_with_rand_reset has 6 failures.

0.aes_stress_all_with_rand_reset.35283082454884671288508131472449830561672385065841955457763293460740904489196
Line 1504, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 4949205878 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 4949205878 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.19314889616457356926228578359115419806277346871276697680439549915480380595790
Line 1741, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2258311544 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 2258311544 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 3 failures:

Test aes_stress_all_with_rand_reset has 3 failures.

2.aes_stress_all_with_rand_reset.33749852635733200232118012058300017658918181218037068410570441346309254344369
Line 1127, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 511531024 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 511531024 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

7.aes_stress_all_with_rand_reset.17145594410459586771848810186325836125203049620846620297930620085048073599376
Line 1078, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/7.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1088707401 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1088707401 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 3 failures:
- Test aes_core_fi has 3 failures.
  - 36.aes_core_fi.107665890044831785018943525715610055289967646121519412033873452738153544183466
    Line 317, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/36.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10001935631 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10001935631 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 47.aes_core_fi.9247079050281571319040026302471168194608067989904988557069320593421129996380
    Line 318, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/47.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10004501987 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10004501987 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=*) == * has 2 failures:
- Test aes_core_fi has 2 failures.
  - 56.aes_core_fi.22362527826591894737145783930774537578250647917847338716398883170832756750597
    Line 312, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/56.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10005519147 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0xf14afe84) == 0x0
  UVM_INFO @ 10005519147 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 67.aes_core_fi.51134586937159967498345466582251414076313286041535086290436134769449979314591
    Line 314, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/67.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10039272852 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0x28bf3e84) == 0x0
  UVM_INFO @ 10039272852 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:816) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test aes_csr_mem_rw_with_rand_reset has 1 failures.
  - 2.aes_csr_mem_rw_with_rand_reset.72810850636628969520926038388794882548485138414626944675524987524567800271802
    Line 285, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/2.aes_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 111544708 ps: (cip_base_vseq.sv:816) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 111544708 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,984): Assertion AesSecCmDataRegLocalEscIv has failed (* cycles, starting * PS) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 4.aes_stress_all_with_rand_reset.28879058302791634233224841649834455451877894838170712833305139253942748901010
    Line 1463, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/4.aes_stress_all_with_rand_reset/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,984): (time 8777094252 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 8777082758 PS)
  UVM_ERROR @ 8777094252 ps: (aes_core.sv:984) [ASSERT FAILED] AesSecCmDataRegLocalEscIv
  UVM_INFO @ 8777094252 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_readability_vseq.sv:121) virtual_sequencer [aes_readability_vseq] ----| data out reg was not cleared |---- has 1 failures:
- Test aes_readability has 1 failures.
  - 40.aes_readability.48712596941246874176737709820604477496799529372653903556690564057211726474732
    Line 307, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/40.aes_readability/latest/run.log
```
  UVM_FATAL @  43799292 ps: (aes_readability_vseq.sv:121) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.aes_readability_vseq] ----| data out reg was not cleared |----
  UVM_INFO @  43799292 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```