AES/UNMASKED Simulation Results

Thursday February 29 2024 20:02:24 UTC

GitHub Revision: `e0c4026501`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 37435771356197831901593787335841447308974032110687249165442170486932885997295

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	8.000s	71.339us	1	1	100.00
V1	smoke	aes_smoke	12.000s	55.233us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	60.143us	5	5	100.00
V1	csr_rw	aes_csr_rw	8.000s	63.619us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	9.000s	522.970us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	271.330us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	8.000s	68.351us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	8.000s	63.619us	20	20	100.00
		aes_csr_aliasing	5.000s	271.330us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	12.000s	55.233us	50	50	100.00
		aes_config_error	8.000s	95.809us	50	50	100.00
		aes_stress	15.000s	105.955us	50	50	100.00
V2	key_length	aes_smoke	12.000s	55.233us	50	50	100.00
		aes_config_error	8.000s	95.809us	50	50	100.00
		aes_stress	15.000s	105.955us	50	50	100.00
V2	back2back	aes_stress	15.000s	105.955us	50	50	100.00
		aes_b2b	13.000s	347.134us	50	50	100.00
V2	backpressure	aes_stress	15.000s	105.955us	50	50	100.00
V2	multi_message	aes_smoke	12.000s	55.233us	50	50	100.00
		aes_config_error	8.000s	95.809us	50	50	100.00
		aes_stress	15.000s	105.955us	50	50	100.00
		aes_alert_reset	13.000s	82.705us	50	50	100.00
V2	failure_test	aes_man_cfg_err	8.000s	59.031us	50	50	100.00
		aes_config_error	8.000s	95.809us	50	50	100.00
		aes_alert_reset	13.000s	82.705us	50	50	100.00
V2	trigger_clear_test	aes_clear	10.000s	93.256us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	6.000s	597.307us	1	1	100.00
V2	reset_recovery	aes_alert_reset	13.000s	82.705us	50	50	100.00
V2	stress	aes_stress	15.000s	105.955us	50	50	100.00
V2	sideload	aes_stress	15.000s	105.955us	50	50	100.00
		aes_sideload	13.000s	59.402us	50	50	100.00
V2	deinitialization	aes_deinit	14.000s	96.202us	50	50	100.00
V2	stress_all	aes_stress_all	31.000s	1.547ms	10	10	100.00
V2	alert_test	aes_alert_test	8.000s	93.307us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	6.000s	150.911us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	6.000s	150.911us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	60.143us	5	5	100.00
		aes_csr_rw	8.000s	63.619us	20	20	100.00
		aes_csr_aliasing	5.000s	271.330us	5	5	100.00
		aes_same_csr_outstanding	8.000s	77.055us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	60.143us	5	5	100.00
		aes_csr_rw	8.000s	63.619us	20	20	100.00
		aes_csr_aliasing	5.000s	271.330us	5	5	100.00
		aes_same_csr_outstanding	8.000s	77.055us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	9.000s	195.508us	50	50	100.00
V2S	fault_inject	aes_fi	9.000s	98.188us	50	50	100.00
		aes_control_fi	45.000s	31.535ms	280	300	93.33
		aes_cipher_fi	49.000s	63.024ms	316	350	90.29
V2S	shadow_reg_update_error	aes_shadow_reg_errors	3.000s	112.089us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	3.000s	112.089us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	3.000s	112.089us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	3.000s	112.089us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	4.000s	100.048us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	15.000s	826.874us	5	5	100.00
		aes_tl_intg_err	6.000s	560.751us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	6.000s	560.751us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	13.000s	82.705us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	3.000s	112.089us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	12.000s	55.233us	50	50	100.00
		aes_stress	15.000s	105.955us	50	50	100.00
		aes_alert_reset	13.000s	82.705us	50	50	100.00
		aes_core_fi	1.150m	10.010ms	65	70	92.86
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	3.000s	112.089us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	13.000s	64.402us	50	50	100.00
		aes_stress	15.000s	105.955us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	15.000s	105.955us	50	50	100.00
		aes_sideload	13.000s	59.402us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	13.000s	64.402us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	13.000s	64.402us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	13.000s	64.402us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	13.000s	64.402us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	13.000s	64.402us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	15.000s	105.955us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	15.000s	105.955us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	9.000s	98.188us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	9.000s	98.188us	50	50	100.00
		aes_control_fi	45.000s	31.535ms	280	300	93.33
		aes_cipher_fi	49.000s	63.024ms	316	350	90.29
		aes_ctr_fi	8.000s	57.900us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	9.000s	98.188us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	9.000s	98.188us	50	50	100.00
		aes_control_fi	45.000s	31.535ms	280	300	93.33
		aes_cipher_fi	49.000s	63.024ms	316	350	90.29
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	49.000s	63.024ms	316	350	90.29
V2S	sec_cm_ctr_fsm_sparse	aes_fi	9.000s	98.188us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	9.000s	98.188us	50	50	100.00
		aes_control_fi	45.000s	31.535ms	280	300	93.33
		aes_ctr_fi	8.000s	57.900us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	9.000s	98.188us	50	50	100.00
		aes_control_fi	45.000s	31.535ms	280	300	93.33
		aes_cipher_fi	49.000s	63.024ms	316	350	90.29
		aes_ctr_fi	8.000s	57.900us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	13.000s	82.705us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	9.000s	98.188us	50	50	100.00
		aes_control_fi	45.000s	31.535ms	280	300	93.33
		aes_cipher_fi	49.000s	63.024ms	316	350	90.29
		aes_ctr_fi	8.000s	57.900us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	9.000s	98.188us	50	50	100.00
		aes_control_fi	45.000s	31.535ms	280	300	93.33
		aes_cipher_fi	49.000s	63.024ms	316	350	90.29
		aes_ctr_fi	8.000s	57.900us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	9.000s	98.188us	50	50	100.00
		aes_control_fi	45.000s	31.535ms	280	300	93.33
		aes_ctr_fi	8.000s	57.900us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	9.000s	98.188us	50	50	100.00
		aes_control_fi	45.000s	31.535ms	280	300	93.33
		aes_cipher_fi	49.000s	63.024ms	316	350	90.29
V2S		TOTAL			926	985	94.01
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	4.333m	43.889ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1533	1602	95.69

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	13	100.00
V2S	11	11	8	72.73
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.18	97.38	94.07	98.87	93.70	97.64	93.33	98.66	96.41

Failure Buckets

Job aes_unmasked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 30 failures:
- Test aes_cipher_fi has 21 failures.
  - 16.aes_cipher_fi.52889558536876606168867322213934153080231495236786335442798292685272273473223
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/16.aes_cipher_fi/latest/run.log
```
  Job ID: smart:d2d3d30b-33be-4b24-bf87-b4a49878e6b0
```
  - 23.aes_cipher_fi.53576416072490432264391733195237879023267436771837782495865043975905774296354
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/23.aes_cipher_fi/latest/run.log
```
  Job ID: smart:0dd89635-a8f3-4b37-a6f3-5305ef458028
```
  - ... and 19 more failures.
- Test aes_control_fi has 9 failures.
  - 70.aes_control_fi.90539007247235320308133653492970725569458227898455982489900748793724620467220
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/70.aes_control_fi/latest/run.log
```
  Job ID: smart:c0aa8b0e-187b-45a3-b461-2d08c1f46e41
```
  - 109.aes_control_fi.95975252289476018438722435444974415967520800143964555325056511624826701022713
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/109.aes_control_fi/latest/run.log
```
  Job ID: smart:cfd28629-b94c-4bd6-b2a5-9bdf31c72a3f
```
  - ... and 7 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 13 failures:
- Test aes_cipher_fi has 13 failures.
  - 13.aes_cipher_fi.93424458020928660749686629038274822873365202023563580631386522074395491409922
    Line 318, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/13.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10002620317 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10002620317 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 22.aes_cipher_fi.114502868833900879004646287499669024809475630407969457105351415750576797166088
    Line 317, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/22.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10011051362 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10011051362 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 11 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 11 failures:
- Test aes_control_fi has 11 failures.
  - 26.aes_control_fi.81360568730849922554508633872710124415031665826778618944213744700354189989358
    Line 318, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/26.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10007581613 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10007581613 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 100.aes_control_fi.18278261326098955114439091389621675191493915028154730258355655596106739064953
    Line 326, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/100.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10007594034 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10007594034 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 9 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 9 failures:

Test aes_stress_all_with_rand_reset has 9 failures.

1.aes_stress_all_with_rand_reset.52222591181415624999382616125542523761062918513749514057240469161516560370994
Line 1785, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 960887334 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 960887334 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.aes_stress_all_with_rand_reset.37580418356536380067332606398985701021881623882619055677169801073224541042607
Line 1854, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1411841172 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1411841172 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 7 more failures.

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 3 failures:
- Test aes_core_fi has 3 failures.
  - 51.aes_core_fi.106635399347658682886675335990920613302279225986180553113261591192918361006682
    Line 313, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/51.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10006173014 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006173014 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 65.aes_core_fi.1896471797744638233631481957493626697754248314919286869960339945658120041404
    Line 322, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/65.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10007067409 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10007067409 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL (aes_core_fi_vseq.sv:89) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_core_fi has 2 failures.
  - 24.aes_core_fi.22049193607577214316694295216855429359574549898546947778558778300339505814828
    Line 315, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/24.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10010021010 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10010021010 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 53.aes_core_fi.42915353323757372355207153072959767613507275773919831280914662325388471369521
    Line 315, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/53.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10047958549 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10047958549 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 0.aes_stress_all_with_rand_reset.442622043821188951141307713198337385826355229296832357270888188790318663700
    Line 1092, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1070684803 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1070684803 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```