c30684b3ca
Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
---|---|---|---|---|---|---|---|
V1 | wake_up | aes_wake_up | 2.000s | 73.953us | 1 | 1 | 100.00 |
V1 | smoke | aes_smoke | 8.000s | 74.510us | 50 | 50 | 100.00 |
V1 | csr_hw_reset | aes_csr_hw_reset | 3.000s | 69.331us | 5 | 5 | 100.00 |
V1 | csr_rw | aes_csr_rw | 4.000s | 138.374us | 20 | 20 | 100.00 |
V1 | csr_bit_bash | aes_csr_bit_bash | 15.000s | 989.338us | 5 | 5 | 100.00 |
V1 | csr_aliasing | aes_csr_aliasing | 5.000s | 260.298us | 5 | 5 | 100.00 |
V1 | csr_mem_rw_with_rand_reset | aes_csr_mem_rw_with_rand_reset | 4.000s | 92.405us | 19 | 20 | 95.00 |
V1 | regwen_csr_and_corresponding_lockable_csr | aes_csr_rw | 4.000s | 138.374us | 20 | 20 | 100.00 |
aes_csr_aliasing | 5.000s | 260.298us | 5 | 5 | 100.00 | ||
V1 | TOTAL | 105 | 106 | 99.06 | |||
V2 | algorithm | aes_smoke | 8.000s | 74.510us | 50 | 50 | 100.00 |
aes_config_error | 9.000s | 124.235us | 50 | 50 | 100.00 | ||
aes_stress | 10.000s | 167.456us | 50 | 50 | 100.00 | ||
V2 | key_length | aes_smoke | 8.000s | 74.510us | 50 | 50 | 100.00 |
aes_config_error | 9.000s | 124.235us | 50 | 50 | 100.00 | ||
aes_stress | 10.000s | 167.456us | 50 | 50 | 100.00 | ||
V2 | back2back | aes_stress | 10.000s | 167.456us | 50 | 50 | 100.00 |
aes_b2b | 13.000s | 281.127us | 50 | 50 | 100.00 | ||
V2 | backpressure | aes_stress | 10.000s | 167.456us | 50 | 50 | 100.00 |
V2 | multi_message | aes_smoke | 8.000s | 74.510us | 50 | 50 | 100.00 |
aes_config_error | 9.000s | 124.235us | 50 | 50 | 100.00 | ||
aes_stress | 10.000s | 167.456us | 50 | 50 | 100.00 | ||
aes_alert_reset | 20.000s | 181.311us | 50 | 50 | 100.00 | ||
V2 | failure_test | aes_man_cfg_err | 18.000s | 212.644us | 50 | 50 | 100.00 |
aes_config_error | 9.000s | 124.235us | 50 | 50 | 100.00 | ||
aes_alert_reset | 20.000s | 181.311us | 50 | 50 | 100.00 | ||
V2 | trigger_clear_test | aes_clear | 14.000s | 133.245us | 50 | 50 | 100.00 |
V2 | nist_test_vectors | aes_nist_vectors | 5.000s | 197.258us | 1 | 1 | 100.00 |
V2 | reset_recovery | aes_alert_reset | 20.000s | 181.311us | 50 | 50 | 100.00 |
V2 | stress | aes_stress | 10.000s | 167.456us | 50 | 50 | 100.00 |
V2 | sideload | aes_stress | 10.000s | 167.456us | 50 | 50 | 100.00 |
aes_sideload | 9.000s | 126.630us | 50 | 50 | 100.00 | ||
V2 | deinitialization | aes_deinit | 14.000s | 296.920us | 50 | 50 | 100.00 |
V2 | stress_all | aes_stress_all | 33.000s | 10.568ms | 10 | 10 | 100.00 |
V2 | alert_test | aes_alert_test | 8.000s | 123.348us | 50 | 50 | 100.00 |
V2 | tl_d_oob_addr_access | aes_tl_errors | 10.000s | 90.434us | 20 | 20 | 100.00 |
V2 | tl_d_illegal_access | aes_tl_errors | 10.000s | 90.434us | 20 | 20 | 100.00 |
V2 | tl_d_outstanding_access | aes_csr_hw_reset | 3.000s | 69.331us | 5 | 5 | 100.00 |
aes_csr_rw | 4.000s | 138.374us | 20 | 20 | 100.00 | ||
aes_csr_aliasing | 5.000s | 260.298us | 5 | 5 | 100.00 | ||
aes_same_csr_outstanding | 8.000s | 59.631us | 20 | 20 | 100.00 | ||
V2 | tl_d_partial_access | aes_csr_hw_reset | 3.000s | 69.331us | 5 | 5 | 100.00 |
aes_csr_rw | 4.000s | 138.374us | 20 | 20 | 100.00 | ||
aes_csr_aliasing | 5.000s | 260.298us | 5 | 5 | 100.00 | ||
aes_same_csr_outstanding | 8.000s | 59.631us | 20 | 20 | 100.00 | ||
V2 | TOTAL | 501 | 501 | 100.00 | |||
V2S | reseeding | aes_reseed | 14.000s | 75.847us | 50 | 50 | 100.00 |
V2S | fault_inject | aes_fi | 13.000s | 114.715us | 50 | 50 | 100.00 |
aes_control_fi | 48.000s | 105.016ms | 274 | 300 | 91.33 | ||
aes_cipher_fi | 49.000s | 10.005ms | 318 | 350 | 90.86 | ||
V2S | shadow_reg_update_error | aes_shadow_reg_errors | 8.000s | 147.675us | 20 | 20 | 100.00 |
V2S | shadow_reg_read_clear_staged_value | aes_shadow_reg_errors | 8.000s | 147.675us | 20 | 20 | 100.00 |
V2S | shadow_reg_storage_error | aes_shadow_reg_errors | 8.000s | 147.675us | 20 | 20 | 100.00 |
V2S | shadowed_reset_glitch | aes_shadow_reg_errors | 8.000s | 147.675us | 20 | 20 | 100.00 |
V2S | shadow_reg_update_error_with_csr_rw | aes_shadow_reg_errors_with_csr_rw | 4.000s | 251.018us | 20 | 20 | 100.00 |
V2S | tl_intg_err | aes_sec_cm | 10.000s | 2.256ms | 5 | 5 | 100.00 |
aes_tl_intg_err | 8.000s | 125.639us | 20 | 20 | 100.00 | ||
V2S | sec_cm_bus_integrity | aes_tl_intg_err | 8.000s | 125.639us | 20 | 20 | 100.00 |
V2S | sec_cm_lc_escalate_en_intersig_mubi | aes_alert_reset | 20.000s | 181.311us | 50 | 50 | 100.00 |
V2S | sec_cm_main_config_shadow | aes_shadow_reg_errors | 8.000s | 147.675us | 20 | 20 | 100.00 |
V2S | sec_cm_main_config_sparse | aes_smoke | 8.000s | 74.510us | 50 | 50 | 100.00 |
aes_stress | 10.000s | 167.456us | 50 | 50 | 100.00 | ||
aes_alert_reset | 20.000s | 181.311us | 50 | 50 | 100.00 | ||
aes_core_fi | 1.000m | 10.012ms | 66 | 70 | 94.29 | ||
V2S | sec_cm_aux_config_shadow | aes_shadow_reg_errors | 8.000s | 147.675us | 20 | 20 | 100.00 |
V2S | sec_cm_aux_config_regwen | aes_readability | 13.000s | 67.286us | 50 | 50 | 100.00 |
aes_stress | 10.000s | 167.456us | 50 | 50 | 100.00 | ||
V2S | sec_cm_key_sideload | aes_stress | 10.000s | 167.456us | 50 | 50 | 100.00 |
aes_sideload | 9.000s | 126.630us | 50 | 50 | 100.00 | ||
V2S | sec_cm_key_sw_unreadable | aes_readability | 13.000s | 67.286us | 50 | 50 | 100.00 |
V2S | sec_cm_data_reg_sw_unreadable | aes_readability | 13.000s | 67.286us | 50 | 50 | 100.00 |
V2S | sec_cm_key_sec_wipe | aes_readability | 13.000s | 67.286us | 50 | 50 | 100.00 |
V2S | sec_cm_iv_config_sec_wipe | aes_readability | 13.000s | 67.286us | 50 | 50 | 100.00 |
V2S | sec_cm_data_reg_sec_wipe | aes_readability | 13.000s | 67.286us | 50 | 50 | 100.00 |
V2S | sec_cm_data_reg_key_sca | aes_stress | 10.000s | 167.456us | 50 | 50 | 100.00 |
V2S | sec_cm_key_masking | aes_stress | 10.000s | 167.456us | 50 | 50 | 100.00 |
V2S | sec_cm_main_fsm_sparse | aes_fi | 13.000s | 114.715us | 50 | 50 | 100.00 |
V2S | sec_cm_main_fsm_redun | aes_fi | 13.000s | 114.715us | 50 | 50 | 100.00 |
aes_control_fi | 48.000s | 105.016ms | 274 | 300 | 91.33 | ||
aes_cipher_fi | 49.000s | 10.005ms | 318 | 350 | 90.86 | ||
aes_ctr_fi | 16.000s | 104.221us | 50 | 50 | 100.00 | ||
V2S | sec_cm_cipher_fsm_sparse | aes_fi | 13.000s | 114.715us | 50 | 50 | 100.00 |
V2S | sec_cm_cipher_fsm_redun | aes_fi | 13.000s | 114.715us | 50 | 50 | 100.00 |
aes_control_fi | 48.000s | 105.016ms | 274 | 300 | 91.33 | ||
aes_cipher_fi | 49.000s | 10.005ms | 318 | 350 | 90.86 | ||
V2S | sec_cm_cipher_ctr_redun | aes_cipher_fi | 49.000s | 10.005ms | 318 | 350 | 90.86 |
V2S | sec_cm_ctr_fsm_sparse | aes_fi | 13.000s | 114.715us | 50 | 50 | 100.00 |
V2S | sec_cm_ctr_fsm_redun | aes_fi | 13.000s | 114.715us | 50 | 50 | 100.00 |
aes_control_fi | 48.000s | 105.016ms | 274 | 300 | 91.33 | ||
aes_ctr_fi | 16.000s | 104.221us | 50 | 50 | 100.00 | ||
V2S | sec_cm_ctrl_sparse | aes_fi | 13.000s | 114.715us | 50 | 50 | 100.00 |
aes_control_fi | 48.000s | 105.016ms | 274 | 300 | 91.33 | ||
aes_cipher_fi | 49.000s | 10.005ms | 318 | 350 | 90.86 | ||
aes_ctr_fi | 16.000s | 104.221us | 50 | 50 | 100.00 | ||
V2S | sec_cm_main_fsm_global_esc | aes_alert_reset | 20.000s | 181.311us | 50 | 50 | 100.00 |
V2S | sec_cm_main_fsm_local_esc | aes_fi | 13.000s | 114.715us | 50 | 50 | 100.00 |
aes_control_fi | 48.000s | 105.016ms | 274 | 300 | 91.33 | ||
aes_cipher_fi | 49.000s | 10.005ms | 318 | 350 | 90.86 | ||
aes_ctr_fi | 16.000s | 104.221us | 50 | 50 | 100.00 | ||
V2S | sec_cm_cipher_fsm_local_esc | aes_fi | 13.000s | 114.715us | 50 | 50 | 100.00 |
aes_control_fi | 48.000s | 105.016ms | 274 | 300 | 91.33 | ||
aes_cipher_fi | 49.000s | 10.005ms | 318 | 350 | 90.86 | ||
aes_ctr_fi | 16.000s | 104.221us | 50 | 50 | 100.00 | ||
V2S | sec_cm_ctr_fsm_local_esc | aes_fi | 13.000s | 114.715us | 50 | 50 | 100.00 |
aes_control_fi | 48.000s | 105.016ms | 274 | 300 | 91.33 | ||
aes_ctr_fi | 16.000s | 104.221us | 50 | 50 | 100.00 | ||
V2S | sec_cm_data_reg_local_esc | aes_fi | 13.000s | 114.715us | 50 | 50 | 100.00 |
aes_control_fi | 48.000s | 105.016ms | 274 | 300 | 91.33 | ||
aes_cipher_fi | 49.000s | 10.005ms | 318 | 350 | 90.86 | ||
V2S | TOTAL | 923 | 985 | 93.71 | |||
V3 | stress_all_with_rand_reset | aes_stress_all_with_rand_reset | 45.000s | 11.141ms | 0 | 10 | 0.00 |
V3 | TOTAL | 0 | 10 | 0.00 | |||
TOTAL | 1529 | 1602 | 95.44 |
Items | Total | Written | Passing | Progress |
---|---|---|---|---|
V1 | 7 | 7 | 6 | 85.71 |
V2 | 13 | 13 | 13 | 100.00 |
V2S | 11 | 11 | 8 | 72.73 |
V3 | 1 | 1 | 0 | 0.00 |
Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
---|---|---|---|---|---|---|---|---|
97.22 | 97.49 | 94.33 | 98.87 | 93.76 | 97.72 | 93.33 | 98.85 | 95.41 |
Job aes_unmasked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out
has 34 failures:
0.aes_control_fi.88713378740880444571580999253257936101803341825725863626923817957628814693238
Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_control_fi/latest/run.log
Job ID: smart:229a9e4f-b7ab-47af-bf77-e249b4db1302
31.aes_control_fi.5542945277274629221952535040187212385812392560898122362422550830600144566764
Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/31.aes_control_fi/latest/run.log
Job ID: smart:fe999147-32cf-410a-af0f-b07a4628a672
... and 13 more failures.
4.aes_cipher_fi.11379156777727841461368167430896670228464030956809711071820303622297338698232
Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/4.aes_cipher_fi/latest/run.log
Job ID: smart:e0c7749a-545c-4044-ba91-8da7f3d3149d
63.aes_cipher_fi.55897954065238405255635577139688751892389754581424379546951414272679877014853
Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/63.aes_cipher_fi/latest/run.log
Job ID: smart:f9f974ef-8d66-4167-98ef-2d102d6531cd
... and 17 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred!
has 13 failures:
39.aes_cipher_fi.87402520679233725786923905121523783325625948473409119660674088983425409736955
Line 316, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/39.aes_cipher_fi/latest/run.log
UVM_FATAL @ 10002058349 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
UVM_INFO @ 10002058349 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
134.aes_cipher_fi.38925274671583480981848887909687496575062519327246682679153892190300940283637
Line 319, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/134.aes_cipher_fi/latest/run.log
UVM_FATAL @ 10023807885 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
UVM_INFO @ 10023807885 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 11 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred!
has 11 failures:
18.aes_control_fi.61492979893597774151440554484574311275363733994616936485587183618211964121431
Line 323, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/18.aes_control_fi/latest/run.log
UVM_FATAL @ 10006084246 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
UVM_INFO @ 10006084246 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
85.aes_control_fi.94689843714735397102419291996702143468308627852006508774564489637736463170484
Line 322, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/85.aes_control_fi/latest/run.log
UVM_FATAL @ 10007401738 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
UVM_INFO @ 10007401738 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 9 more failures.
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
has 6 failures:
0.aes_stress_all_with_rand_reset.77892874797677359069517604048137506262180569818505051802096963945735650521539
Line 788, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 542390202 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
UVM_INFO @ 542390202 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.aes_stress_all_with_rand_reset.61743559222117287618796543541577825910383594848923836952204901003462857043748
Line 1236, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 7527976726 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
UVM_INFO @ 7527976726 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
has 4 failures:
2.aes_stress_all_with_rand_reset.2888134685337151294179411091176553417313571537338334605383122685635811581204
Line 1722, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1945568409 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
UVM_INFO @ 1945568409 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.aes_stress_all_with_rand_reset.110953994038479976079732795446626263565996763005341992640355513724750628913863
Line 836, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/5.aes_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 442613366 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
UVM_INFO @ 442613366 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_FATAL (aes_core_fi_vseq.sv:89) [aes_core_fi_vseq] wait timeout occurred!
has 2 failures:
7.aes_core_fi.18591510687197827354095080884531460188925761540799687534885979266363582438138
Line 316, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/7.aes_core_fi/latest/run.log
UVM_FATAL @ 10028382565 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
UVM_INFO @ 10028382565 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
45.aes_core_fi.80135783845561966102039621298172416940162378679219038441815542243518644146760
Line 316, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/45.aes_core_fi/latest/run.log
UVM_FATAL @ 10012010188 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
UVM_INFO @ 10012010188 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred!
has 2 failures:
17.aes_core_fi.41632644779713542445942938902700654719182009915377572779688236665784362058338
Line 317, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/17.aes_core_fi/latest/run.log
UVM_FATAL @ 10001993952 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
UVM_INFO @ 10001993952 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
29.aes_core_fi.69394616111051291415143217896278986058182388759084684601482224259947288870975
Line 314, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/29.aes_core_fi/latest/run.log
UVM_FATAL @ 10003697429 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
UVM_INFO @ 10003697429 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:828) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
has 1 failures:
13.aes_csr_mem_rw_with_rand_reset.85081644527092914090286816838531425184323161277586733033332317144058612825695
Line 292, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/13.aes_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 120377672 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 120377672 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---