AES/UNMASKED Simulation Results

Tuesday March 05 2024 20:02:48 UTC

GitHub Revision: c30684b3ca

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 61875946985821051720030118255902427822651914203242934898647746371735217685454

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 wake_up aes_wake_up 2.000s 73.953us 1 1 100.00
V1 smoke aes_smoke 8.000s 74.510us 50 50 100.00
V1 csr_hw_reset aes_csr_hw_reset 3.000s 69.331us 5 5 100.00
V1 csr_rw aes_csr_rw 4.000s 138.374us 20 20 100.00
V1 csr_bit_bash aes_csr_bit_bash 15.000s 989.338us 5 5 100.00
V1 csr_aliasing aes_csr_aliasing 5.000s 260.298us 5 5 100.00
V1 csr_mem_rw_with_rand_reset aes_csr_mem_rw_with_rand_reset 4.000s 92.405us 19 20 95.00
V1 regwen_csr_and_corresponding_lockable_csr aes_csr_rw 4.000s 138.374us 20 20 100.00
aes_csr_aliasing 5.000s 260.298us 5 5 100.00
V1 TOTAL 105 106 99.06
V2 algorithm aes_smoke 8.000s 74.510us 50 50 100.00
aes_config_error 9.000s 124.235us 50 50 100.00
aes_stress 10.000s 167.456us 50 50 100.00
V2 key_length aes_smoke 8.000s 74.510us 50 50 100.00
aes_config_error 9.000s 124.235us 50 50 100.00
aes_stress 10.000s 167.456us 50 50 100.00
V2 back2back aes_stress 10.000s 167.456us 50 50 100.00
aes_b2b 13.000s 281.127us 50 50 100.00
V2 backpressure aes_stress 10.000s 167.456us 50 50 100.00
V2 multi_message aes_smoke 8.000s 74.510us 50 50 100.00
aes_config_error 9.000s 124.235us 50 50 100.00
aes_stress 10.000s 167.456us 50 50 100.00
aes_alert_reset 20.000s 181.311us 50 50 100.00
V2 failure_test aes_man_cfg_err 18.000s 212.644us 50 50 100.00
aes_config_error 9.000s 124.235us 50 50 100.00
aes_alert_reset 20.000s 181.311us 50 50 100.00
V2 trigger_clear_test aes_clear 14.000s 133.245us 50 50 100.00
V2 nist_test_vectors aes_nist_vectors 5.000s 197.258us 1 1 100.00
V2 reset_recovery aes_alert_reset 20.000s 181.311us 50 50 100.00
V2 stress aes_stress 10.000s 167.456us 50 50 100.00
V2 sideload aes_stress 10.000s 167.456us 50 50 100.00
aes_sideload 9.000s 126.630us 50 50 100.00
V2 deinitialization aes_deinit 14.000s 296.920us 50 50 100.00
V2 stress_all aes_stress_all 33.000s 10.568ms 10 10 100.00
V2 alert_test aes_alert_test 8.000s 123.348us 50 50 100.00
V2 tl_d_oob_addr_access aes_tl_errors 10.000s 90.434us 20 20 100.00
V2 tl_d_illegal_access aes_tl_errors 10.000s 90.434us 20 20 100.00
V2 tl_d_outstanding_access aes_csr_hw_reset 3.000s 69.331us 5 5 100.00
aes_csr_rw 4.000s 138.374us 20 20 100.00
aes_csr_aliasing 5.000s 260.298us 5 5 100.00
aes_same_csr_outstanding 8.000s 59.631us 20 20 100.00
V2 tl_d_partial_access aes_csr_hw_reset 3.000s 69.331us 5 5 100.00
aes_csr_rw 4.000s 138.374us 20 20 100.00
aes_csr_aliasing 5.000s 260.298us 5 5 100.00
aes_same_csr_outstanding 8.000s 59.631us 20 20 100.00
V2 TOTAL 501 501 100.00
V2S reseeding aes_reseed 14.000s 75.847us 50 50 100.00
V2S fault_inject aes_fi 13.000s 114.715us 50 50 100.00
aes_control_fi 48.000s 105.016ms 274 300 91.33
aes_cipher_fi 49.000s 10.005ms 318 350 90.86
V2S shadow_reg_update_error aes_shadow_reg_errors 8.000s 147.675us 20 20 100.00
V2S shadow_reg_read_clear_staged_value aes_shadow_reg_errors 8.000s 147.675us 20 20 100.00
V2S shadow_reg_storage_error aes_shadow_reg_errors 8.000s 147.675us 20 20 100.00
V2S shadowed_reset_glitch aes_shadow_reg_errors 8.000s 147.675us 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw aes_shadow_reg_errors_with_csr_rw 4.000s 251.018us 20 20 100.00
V2S tl_intg_err aes_sec_cm 10.000s 2.256ms 5 5 100.00
aes_tl_intg_err 8.000s 125.639us 20 20 100.00
V2S sec_cm_bus_integrity aes_tl_intg_err 8.000s 125.639us 20 20 100.00
V2S sec_cm_lc_escalate_en_intersig_mubi aes_alert_reset 20.000s 181.311us 50 50 100.00
V2S sec_cm_main_config_shadow aes_shadow_reg_errors 8.000s 147.675us 20 20 100.00
V2S sec_cm_main_config_sparse aes_smoke 8.000s 74.510us 50 50 100.00
aes_stress 10.000s 167.456us 50 50 100.00
aes_alert_reset 20.000s 181.311us 50 50 100.00
aes_core_fi 1.000m 10.012ms 66 70 94.29
V2S sec_cm_aux_config_shadow aes_shadow_reg_errors 8.000s 147.675us 20 20 100.00
V2S sec_cm_aux_config_regwen aes_readability 13.000s 67.286us 50 50 100.00
aes_stress 10.000s 167.456us 50 50 100.00
V2S sec_cm_key_sideload aes_stress 10.000s 167.456us 50 50 100.00
aes_sideload 9.000s 126.630us 50 50 100.00
V2S sec_cm_key_sw_unreadable aes_readability 13.000s 67.286us 50 50 100.00
V2S sec_cm_data_reg_sw_unreadable aes_readability 13.000s 67.286us 50 50 100.00
V2S sec_cm_key_sec_wipe aes_readability 13.000s 67.286us 50 50 100.00
V2S sec_cm_iv_config_sec_wipe aes_readability 13.000s 67.286us 50 50 100.00
V2S sec_cm_data_reg_sec_wipe aes_readability 13.000s 67.286us 50 50 100.00
V2S sec_cm_data_reg_key_sca aes_stress 10.000s 167.456us 50 50 100.00
V2S sec_cm_key_masking aes_stress 10.000s 167.456us 50 50 100.00
V2S sec_cm_main_fsm_sparse aes_fi 13.000s 114.715us 50 50 100.00
V2S sec_cm_main_fsm_redun aes_fi 13.000s 114.715us 50 50 100.00
aes_control_fi 48.000s 105.016ms 274 300 91.33
aes_cipher_fi 49.000s 10.005ms 318 350 90.86
aes_ctr_fi 16.000s 104.221us 50 50 100.00
V2S sec_cm_cipher_fsm_sparse aes_fi 13.000s 114.715us 50 50 100.00
V2S sec_cm_cipher_fsm_redun aes_fi 13.000s 114.715us 50 50 100.00
aes_control_fi 48.000s 105.016ms 274 300 91.33
aes_cipher_fi 49.000s 10.005ms 318 350 90.86
V2S sec_cm_cipher_ctr_redun aes_cipher_fi 49.000s 10.005ms 318 350 90.86
V2S sec_cm_ctr_fsm_sparse aes_fi 13.000s 114.715us 50 50 100.00
V2S sec_cm_ctr_fsm_redun aes_fi 13.000s 114.715us 50 50 100.00
aes_control_fi 48.000s 105.016ms 274 300 91.33
aes_ctr_fi 16.000s 104.221us 50 50 100.00
V2S sec_cm_ctrl_sparse aes_fi 13.000s 114.715us 50 50 100.00
aes_control_fi 48.000s 105.016ms 274 300 91.33
aes_cipher_fi 49.000s 10.005ms 318 350 90.86
aes_ctr_fi 16.000s 104.221us 50 50 100.00
V2S sec_cm_main_fsm_global_esc aes_alert_reset 20.000s 181.311us 50 50 100.00
V2S sec_cm_main_fsm_local_esc aes_fi 13.000s 114.715us 50 50 100.00
aes_control_fi 48.000s 105.016ms 274 300 91.33
aes_cipher_fi 49.000s 10.005ms 318 350 90.86
aes_ctr_fi 16.000s 104.221us 50 50 100.00
V2S sec_cm_cipher_fsm_local_esc aes_fi 13.000s 114.715us 50 50 100.00
aes_control_fi 48.000s 105.016ms 274 300 91.33
aes_cipher_fi 49.000s 10.005ms 318 350 90.86
aes_ctr_fi 16.000s 104.221us 50 50 100.00
V2S sec_cm_ctr_fsm_local_esc aes_fi 13.000s 114.715us 50 50 100.00
aes_control_fi 48.000s 105.016ms 274 300 91.33
aes_ctr_fi 16.000s 104.221us 50 50 100.00
V2S sec_cm_data_reg_local_esc aes_fi 13.000s 114.715us 50 50 100.00
aes_control_fi 48.000s 105.016ms 274 300 91.33
aes_cipher_fi 49.000s 10.005ms 318 350 90.86
V2S TOTAL 923 985 93.71
V3 stress_all_with_rand_reset aes_stress_all_with_rand_reset 45.000s 11.141ms 0 10 0.00
V3 TOTAL 0 10 0.00
TOTAL 1529 1602 95.44

Testplan Progress

Items Total Written Passing Progress
V1 7 7 6 85.71
V2 13 13 13 100.00
V2S 11 11 8 72.73
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
97.22 97.49 94.33 98.87 93.76 97.72 93.33 98.85 95.41

Failure Buckets

Past Results