AES/UNMASKED Simulation Results

Tuesday March 12 2024 19:02:37 UTC

GitHub Revision: `bc285b7382`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 8078106501385188224785993882809517173695187907049792415947230968390919037084

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	2.000s	83.920us	1	1	100.00
V1	smoke	aes_smoke	5.000s	80.921us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	4.000s	59.157us	5	5	100.00
V1	csr_rw	aes_csr_rw	4.000s	111.910us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	9.000s	724.464us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	561.078us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	4.000s	106.445us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	4.000s	111.910us	20	20	100.00
		aes_csr_aliasing	5.000s	561.078us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	5.000s	80.921us	50	50	100.00
		aes_config_error	5.000s	63.192us	50	50	100.00
		aes_stress	5.000s	102.910us	50	50	100.00
V2	key_length	aes_smoke	5.000s	80.921us	50	50	100.00
		aes_config_error	5.000s	63.192us	50	50	100.00
		aes_stress	5.000s	102.910us	50	50	100.00
V2	back2back	aes_stress	5.000s	102.910us	50	50	100.00
		aes_b2b	11.000s	603.581us	50	50	100.00
V2	backpressure	aes_stress	5.000s	102.910us	50	50	100.00
V2	multi_message	aes_smoke	5.000s	80.921us	50	50	100.00
		aes_config_error	5.000s	63.192us	50	50	100.00
		aes_stress	5.000s	102.910us	50	50	100.00
		aes_alert_reset	5.000s	198.333us	49	50	98.00
V2	failure_test	aes_man_cfg_err	4.000s	61.134us	50	50	100.00
		aes_config_error	5.000s	63.192us	50	50	100.00
		aes_alert_reset	5.000s	198.333us	49	50	98.00
V2	trigger_clear_test	aes_clear	6.000s	307.886us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	7.000s	655.881us	1	1	100.00
V2	reset_recovery	aes_alert_reset	5.000s	198.333us	49	50	98.00
V2	stress	aes_stress	5.000s	102.910us	50	50	100.00
V2	sideload	aes_stress	5.000s	102.910us	50	50	100.00
		aes_sideload	5.000s	299.718us	50	50	100.00
V2	deinitialization	aes_deinit	5.000s	261.660us	50	50	100.00
V2	stress_all	aes_stress_all	36.000s	1.528ms	10	10	100.00
V2	alert_test	aes_alert_test	4.000s	81.771us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	5.000s	114.070us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	5.000s	114.070us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	4.000s	59.157us	5	5	100.00
		aes_csr_rw	4.000s	111.910us	20	20	100.00
		aes_csr_aliasing	5.000s	561.078us	5	5	100.00
		aes_same_csr_outstanding	13.000s	97.734us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	4.000s	59.157us	5	5	100.00
		aes_csr_rw	4.000s	111.910us	20	20	100.00
		aes_csr_aliasing	5.000s	561.078us	5	5	100.00
		aes_same_csr_outstanding	13.000s	97.734us	20	20	100.00
V2		TOTAL			500	501	99.80
V2S	reseeding	aes_reseed	5.000s	832.626us	50	50	100.00
V2S	fault_inject	aes_fi	5.000s	149.764us	49	50	98.00
		aes_control_fi	40.000s	10.010ms	281	300	93.67
		aes_cipher_fi	44.000s	19.241ms	322	350	92.00
V2S	shadow_reg_update_error	aes_shadow_reg_errors	7.000s	65.174us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	7.000s	65.174us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	7.000s	65.174us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	7.000s	65.174us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	4.000s	96.805us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	6.000s	1.427ms	5	5	100.00
		aes_tl_intg_err	5.000s	208.105us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	5.000s	208.105us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	5.000s	198.333us	49	50	98.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	7.000s	65.174us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	5.000s	80.921us	50	50	100.00
		aes_stress	5.000s	102.910us	50	50	100.00
		aes_alert_reset	5.000s	198.333us	49	50	98.00
		aes_core_fi	6.550m	10.012ms	63	70	90.00
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	7.000s	65.174us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	13.000s	71.436us	50	50	100.00
		aes_stress	5.000s	102.910us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	5.000s	102.910us	50	50	100.00
		aes_sideload	5.000s	299.718us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	13.000s	71.436us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	13.000s	71.436us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	13.000s	71.436us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	13.000s	71.436us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	13.000s	71.436us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	5.000s	102.910us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	5.000s	102.910us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	5.000s	149.764us	49	50	98.00
V2S	sec_cm_main_fsm_redun	aes_fi	5.000s	149.764us	49	50	98.00
		aes_control_fi	40.000s	10.010ms	281	300	93.67
		aes_cipher_fi	44.000s	19.241ms	322	350	92.00
		aes_ctr_fi	5.000s	426.224us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	5.000s	149.764us	49	50	98.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	5.000s	149.764us	49	50	98.00
		aes_control_fi	40.000s	10.010ms	281	300	93.67
		aes_cipher_fi	44.000s	19.241ms	322	350	92.00
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	44.000s	19.241ms	322	350	92.00
V2S	sec_cm_ctr_fsm_sparse	aes_fi	5.000s	149.764us	49	50	98.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	5.000s	149.764us	49	50	98.00
		aes_control_fi	40.000s	10.010ms	281	300	93.67
		aes_ctr_fi	5.000s	426.224us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	5.000s	149.764us	49	50	98.00
		aes_control_fi	40.000s	10.010ms	281	300	93.67
		aes_cipher_fi	44.000s	19.241ms	322	350	92.00
		aes_ctr_fi	5.000s	426.224us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	5.000s	198.333us	49	50	98.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	5.000s	149.764us	49	50	98.00
		aes_control_fi	40.000s	10.010ms	281	300	93.67
		aes_cipher_fi	44.000s	19.241ms	322	350	92.00
		aes_ctr_fi	5.000s	426.224us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	5.000s	149.764us	49	50	98.00
		aes_control_fi	40.000s	10.010ms	281	300	93.67
		aes_cipher_fi	44.000s	19.241ms	322	350	92.00
		aes_ctr_fi	5.000s	426.224us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	5.000s	149.764us	49	50	98.00
		aes_control_fi	40.000s	10.010ms	281	300	93.67
		aes_ctr_fi	5.000s	426.224us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	5.000s	149.764us	49	50	98.00
		aes_control_fi	40.000s	10.010ms	281	300	93.67
		aes_cipher_fi	44.000s	19.241ms	322	350	92.00
V2S		TOTAL			930	985	94.42
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	1.750m	14.403ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1536	1602	95.88

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	12	92.31
V2S	11	11	7	63.64
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.20	97.42	94.16	98.87	93.90	97.64	93.33	98.66	95.41

Failure Buckets

Job aes_unmasked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 32 failures:
- Test aes_cipher_fi has 17 failures.
  - 15.aes_cipher_fi.106223261254149766916531246795527960939726257748152965090352828803143903820722
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/15.aes_cipher_fi/latest/run.log
```
  Job ID: smart:780bdc8d-1712-4dab-8d86-8bb628c46b39
```
  - 20.aes_cipher_fi.12900420612391180212960338400315397373082531436964341429206332362569490915385
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/20.aes_cipher_fi/latest/run.log
```
  Job ID: smart:452fb916-72f1-48c3-aedc-1c075a88a2ef
```
  - ... and 15 more failures.
- Test aes_control_fi has 15 failures.
  - 16.aes_control_fi.67323415112173988435194484226985034265240933200298694529533597608400338877446
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/16.aes_control_fi/latest/run.log
```
  Job ID: smart:a023b857-ccfa-4b3c-a6f9-a6bdb842a79f
```
  - 27.aes_control_fi.19265274395765508063826294301692777182566627839950270617432828252270299443591
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/27.aes_control_fi/latest/run.log
```
  Job ID: smart:ab1f81f0-7c4b-4dcb-9ac2-d7a7a295e0b3
```
  - ... and 13 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 11 failures:
- Test aes_cipher_fi has 11 failures.
  - 13.aes_cipher_fi.32731395419042682115098146617764995620588495686144074404705193727654624501113
    Line 324, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/13.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10003726077 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10003726077 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 19.aes_cipher_fi.67929041534595746423544771960799217768747775755362395572223333969397553783412
    Line 313, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/19.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10011815972 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10011815972 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 9 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 7 failures:

Test aes_stress_all_with_rand_reset has 7 failures.

0.aes_stress_all_with_rand_reset.78033496429408475017982893226084623998707985673836339448098602253110564474992
Line 1561, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 4441692685 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 4441692685 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.22041542744970561442830564107425580126356646787221048331984353555099177066722
Line 1261, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 333902197 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 333902197 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 4 failures:
- Test aes_control_fi has 4 failures.
  - 28.aes_control_fi.94144780399137259226208426626017101130197792836718286857709493902082923282220
    Line 325, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/28.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10005110207 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10005110207 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 30.aes_control_fi.90461171311923750900492655954243432675362725433196918717391501778937275482715
    Line 313, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/30.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10018629353 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10018629353 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 4 failures:
- Test aes_core_fi has 4 failures.
  - 50.aes_core_fi.13334009291903837775139569244118061906965014186588927368137647516285829828588
    Line 316, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/50.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10004539469 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10004539469 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 55.aes_core_fi.105663012839956902820736191430185579280709925304989730979239129070020321188765
    Line 312, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/55.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10021129139 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10021129139 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 3 failures:

Test aes_stress_all_with_rand_reset has 3 failures.

3.aes_stress_all_with_rand_reset.54421724130245558583074296699787672937862736899753660746968950393347696348747
Line 1011, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 244826042 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 244826042 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

6.aes_stress_all_with_rand_reset.29660907548611514029393859931851327111168504873773532601312775898308332954576
Line 1522, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/6.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 782810877 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 782810877 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=*) == * has 2 failures:
- Test aes_core_fi has 2 failures.
  - 44.aes_core_fi.28254102472789777356577474611800046683484291115822243484245400059226674497368
    Line 323, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/44.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10011941557 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0xaf0d0684) == 0x0
  UVM_INFO @ 10011941557 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 54.aes_core_fi.86545008489485375947690719830519554418047847846035383843920430569416772076880
    Line 313, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/54.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10052065466 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0xc918684) == 0x0
  UVM_INFO @ 10052065466 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,978): Assertion AesSecCmDataRegLocalEscDataOut has failed (* cycles, starting * PS) has 1 failures:

Test aes_alert_reset has 1 failures.

34.aes_alert_reset.25562598922345792923654320643460188700754208783372806964822080128275382280233
Line 3074, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/34.aes_alert_reset/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,978): (time 32319359 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 32279359 PS)
        ($past(iv_q) != $past(state_done_transposed, 2) ^ $past(data_in_prev_q, 2)))
                                                                                   |
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,984): (time 32319359 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 32279359 PS)
  UVM_ERROR @  32319359 ps: (aes_core.sv:978) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut

UVM_FATAL (aes_fi_vseq.sv:69) virtual_sequencer [aes_fi_vseq] Was Able to finish without clearing reset has 1 failures:
- Test aes_fi has 1 failures.
  - 46.aes_fi.28177017395807465332936078594209058122868319626525830265204994666620758287735
    Line 4476, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/46.aes_fi/latest/run.log
```
  UVM_FATAL @ 434993309 ps: (aes_fi_vseq.sv:69) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.aes_fi_vseq] Was Able to finish without clearing reset
  UVM_INFO @ 434993309 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:89) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 61.aes_core_fi.69626329037313276660617449821347392227504719778358084634655756095293869712840
    Line 312, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/61.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10005383388 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10005383388 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```